All posts by Samuel K. Moore

Stretchy Wearable Patch Allows Two-Way Communication With Robots

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/automaton/robotics/robotics-hardware/stretchy-wearable-patch-allows-twoway-communication-with-robots

Multifunctional metal-oxide semiconductor used to build flexible RRAM, transistors, and sensors

Engineers at the University of Houston are trying to make the melding of humans and machines a little easier on the humans. They’ve developed an easy-to-manufacture flexible electronics patch that, when attached to a human, translates the person’s motion and other commands to a robot and receives temperature feedback from the robot.

Led by University of Houston assistant professor Cunjiang Yu, the team developed transistors, RRAM memory cells, strain sensors, UV-light detectors, temperature sensors, and heaters all using the same set of materials in a low-temperature manufacturing process. They integrated the different devices into a 4-micrometer-thick adhesive plastic patch.

A paper describing the Houston researchers’ work appears this week in Science Advances.

With the patch on the back of a volunteer’s hand, the researchers were able to control a robot hand—causing it to close or open according to what the human’s hand motion did to the patch’s strain sensors. What’s more, they were able to close the human-robot control loop by providing temperature feedback from the robotic hand to the human one using the patch’s integrated heater circuits.

Descartes Labs Built a Top 500 Supercomputer From Amazon Cloud

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/tech-talk/computing/hardware/descartes-labs-built-a-top-500-supercomputer-from-amazon-cloud

Cofounder Mike Warren talks about the future of high-performance computing in a data-rich, cloud computing world

Descartes Labs cofounder Mike Warren has had some notable firsts in his career, and a surprising number have had lasting impact. Back in 1998 for instance, his was the first Linux-based computer fast enough to gain a spot in the coveted Top 500 list of supercomputers. Today, they all run Linux. Now his company, which crunches geospatial and location data to answer hard questions, has achieved something else that may be indicative of where high-performance computing is headed: It’s built the world’s 136th fastest supercomputer using just Amazon Web Services and Descartes Labs’ own software. In 2010, this would have been the most powerful computer on the planet.

Notably, Amazon didn’t do anything special for Descartes. Warren’s firm just plunked down US $5,000 on the company credit card for the use of a “high-network-throughput instance block” consisting of 41,472 processor cores and 157.8 gigabytes of memory. It then worked out some software to make the collection act as a single machine. Running the standard supercomputer test suite, called LinPack, the system reached 1,926.4 teraFLOPS (trillion floating point operations per second). (Amazon itself made an appearance much lower down on the Top 500 list a few years back, but that’s thought to have been for its own dedicated system in which Amazon was the sole user rather than what’s available to the public.)

Intel Shows Off Chip Packaging Powers

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/tech-talk/semiconductors/processors/intel-shows-off-chip-packaging-powers

Three research directions should bind chiplets more tightly together

Packaging has arguably never been a hotter subject. With Moore’s Law no longer providing the oomph it once did, one path to better computing is to connect chips more tightly together within the same package.

At Semicon West earlier this month, Intel showed off three new research efforts in packaging. One combines two of its existing technologies to more tightly integrate chiplets—smaller chips linked together in a package to form the kind of system that would, until recently, be made as a single large chip. Another adds better power delivery to dies at the top of a 3D stack of chips. And the final one is an improvement on Intel’s chiplet-to-chiplet interface called Advanced Interface Bus (AIB).

First Programmable Memristor Computer

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/tech-talk/semiconductors/processors/first-programmable-memristor-computer

Michigan team builds memristors atop standard CMOS logic to demo a system that can do a variety of edge computing AI tasks

Hoping to speed AI and neuromorphic computing and cut down on power consumption, startups, scientists, and established chip companies have all been looking to do more computing in memory rather than in a processor’s computing core. Memristors and other nonvolatile memory seem to lend themselves to the task particularly well. However, most demonstrations of in-memory computing have been in standalone accelerator chips that either are built for a particular type of AI problem or that need the off-chip resources of a separate processor in order to operate. University of Michigan engineers are claiming the first memristor-based programmable computer for AI that can work on all its own.

Buried Power Lines Make Memory Faster

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/nanoclast/semiconductors/devices/buried-power-lines-make-memory-faster

Researchers at imec explore strategy that could make memory more efficient and pack in more transistors

When chipmakers announce that they’ve managed to pack yet more circuits onto a chip, it’s usually the smaller transistor that gets all the attention. But the interconnects that link transistors to form circuits also have to shrink. Now, some of them simply can’t get any smaller without creating some serious consequences for circuit speed and energy consumption.

The problem is perhaps most obvious in SRAM, the most ubiquitous memory on processors today. But researchers at the Belgian nanotech research center imec have come up with a scheme that could keep SRAM performing well and could eventually lead to a way to pack even more transistors onto integrated circuits.

ICs are made by constructing transistors on the silicon and then adding layers of interconnects above them to connect them together. In IEEE Electron Device Letters, the imec team described a way to take the interconnects that power SRAM cells out of those layers and instead bury them in the silicon. They then used the freed-up space to make other key interconnects bigger and thus less resistant. In simulations, the read-from speed of the resulting memory cells was about 31 percent faster than conventional SRAM, and writing to them required 340 millivolts less than what it takes to power memories whose interconnects aren’t buried.

MicroLED Displays Could Show Up in Products as Soon as 2020

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/consumer-electronics/audiovideo/microled-displays-could-show-up-in-products-as-soon-as-2020

Companies have demonstrated striking prototypes. Now they have to master mass production

One of the most striking things about the prototype microLED display that Silicon Valley startup Mojo Vision unveiled in June was its size. At half a millimeter across, it’s barely bigger than a single pixel from the microLED TV prototype Samsung showed off in 2018. That both use versions of the same technology is remarkable, and it portends big potential for screens made of superefficient and bright micrometer-scale gallium nitride LEDs. Impressive prototypes have proliferated during the past year, and now that companies are turning to the hard work of scaling up their manufacturing processes, displays could appear in some products as soon as late next year.

“We’re seeing really good progress on all fronts, and we’re seeing more and more companies coming out with prototypes,” says Eric Virey, an analyst who follows the nascent industry for Yole Développement.

The driving force behind microLED displays remains a combination of brightness and efficiency that LCD and OLED technology can’t come close to. One demo of a smartwatch-size display by Silicon Valley–based Glo shines at 4,000 nits (candelas per square meter) while consuming less than 1 watt. An equivalent LCD display would burn out in seconds trying to meet half that brightness.

The companies involved broadly fit into two categories. Some are making monolithic displays, where the gallium nitride pixels are made as a complete array on a chip and a separate silicon backplane controls those pixels. And others are using “pick and place” technology to transfer individual LEDs or multi-microLED pixels into place on a thin-film-transistor (TFT) backplane. The former is suited to microdisplays for applications like augmented reality and head-up displays. The latter is a better fit for larger displays.

For those in the first camp, a pathway to a high-throughput, high-yield technology that bonds the backplane to the microLED array is key. The United Kingdom’s Plessey Semiconductors demonstrated a throughput-boosting technology recently, by bonding a wafer full of Jasper Display Corp.’s silicon CMOS backplanes to a wafer of its microLED arrays.

New York City’s Lumiode is founded on the idea that such bonding steps aren’t necessary. “When you have to bond two things together, yield is limited by how that bonding happens,” says Vincent Lee, the startup’s CEO.

Instead Lumiode has been developing a process that allows it to build a TFT array on top of a premade GaN microLED array. That has involved developing low-temperature manufacturing processes gentle enough not to damage or degrade the microLEDs. Much of the work this year has been translating that process to a low-volume foundry for production, says Lee.

For Glo, the work has been more about making the microLED fit the current-delivering capabilities of today’s commercial backplanes, like those driving smartphone displays. “Our device design is focused on low current—two orders of magnitude lower than solid-state lighting,” on the order of nanoamps or microamps, explains Glo CEO Fariba Danesh. “This year is the first year people are talking about current. We’ve been talking about that for five years.”

Glo takes those microLEDs and places them on either a CMOS backplane for microdisplays or on a TFT backplane for larger displays using the same technology for any resolution or display size. The company doesn’t talk about its pick-and-place technology, but it is key to commercial products. “Our transfer yields are right now high enough to make some parts; now we are focused on making thousands and then millions of zero-defect panels,” says Danesh.

Others are looking to simplify production by changing what gets picked up and placed down. X-Celeprint’s scheme is to place an integrated pixel chip that contains both CMOS driver circuits and red, green, and blue microLEDs. It’s a multistep process, but it means that the display backplane now needs to be only a simple-to-manufacture network of wires instead of silicon circuitry. Engineers at CEA-Leti, in Grenoble, France, recently demoed a way to simplify that scheme by transferring the microLEDs to the CMOS drivers all at once in a wafer-to-wafer bonding process.

“It’s really too early to pick a winner and know which technology is best,” says Yole’s Virey. “Some of the prototypes are quite impressive, but they are not perfect yet. A lot of additional work is required to go from a prototype to a commercial display. You need to improve your cost, you need to improve your yield, and you need to make an absolutely perfect display each time.”

This article appears in the August 2019 print issue as “MicroLED Displays Expected in 2020.”

First 3D Nanotube and RRAM ICs Come Out of Foundry

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/nanoclast/semiconductors/devices/first-3d-nanotube-and-rram-ics-come-out-of-foundry

SkyWater Technology Foundry produces first wafers in a drive to match performance of cutting-edge silicon chips

Here’s something you don’t see very often at government-sponsored technology meetings—spontaneous applause. It happened at DARPA’s Electronics Resurgence Initiative Summit this week when MIT assistant professor Max Shulaker held up a silicon wafer that is the first step in proving DARPA’s plan to turn a trailing edge foundry into something that can produce chips that can compete—even in a limited sense—with the world’s leading edge foundries.

“This wafer was made just last Friday… and it’s the first monolithic 3D IC ever fabricated within a foundry,” he told the crowd of several hundred engineers Tuesday in Detroit. On the wafer were multiple chips made of a layer of CMOS carbon nanotube transistors and a layer of RRAM memory cells built atop one another and linked together vertically with a dense array of connectors called vias. The idea behind the DARPA-funded project, called 3DSoC, is that chips made with multiple layers of both would have a 50-fold performance advantage over today’s 7-nanometer chips. That’s especially ambitious given that the lithographic process the new chips are based on (the 90-nanometer node) was last cutting-edge back in 2004.

Intel’s Neuromorphic System Hits 8 Million Neurons, 100 Million Coming by 2020

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/tech-talk/robotics/artificial-intelligence/intels-neuromorphic-system-hits-8-million-neurons-100-million-coming-by-2020

Researchers can use the 64-chip Pohoiki Beach system to make systems that learn and see the world more like humans

At the DARPA Electronics Resurgence Initiative Summit today in Detroit, Intel plans to unveil an 8-million-neuron neuromorphic system comprising 64 Loihi research chips—codenamed Pohoiki Beach. Loihi chips are built with an architecture that more closely matches the way the brain works than do chips designed to do deep learning or other forms of AI. For the set of problems that such “spiking neural networks” are particularly good at, Loihi is about 1,000 times as fast as a CPU and 10,000 times as energy efficient. The new 64-Loihi system represents the equivalent of 8-million neurons, but that’s just a step to a 768-chip, 100-million-neuron system that the company plans for the end of 2019.

Intel and its research partners are just beginning to test what massive neural systems like Pohoiki Beach can do, but so far the evidence points to even greater performance and efficiency, says Mike Davies, director of neuromorphic research at Intel.

“We’re quickly accumulating results and data that there are definite benefits… mostly in the domain of efficiency. Virtually every one that we benchmark…we find significant gains in this architecture,” he says.

Applied Materials’ New Memory Machines

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/nanoclast/semiconductors/memory/applied-materials-new-memory-machines

Tools designed to rapidly build embedded MRAM, RRAM, and phase change memories on logic chips expand foundry options

Chip equipment giant Applied Materials wants foundry companies to know that it feels their pain. Continuing down the traditional Moore’s Law path of increasing the density of transistors on a chip is too expensive for all but the three richest players—Intel, Samsung, and TSMC. So to keep the customers coming, other foundries can instead add new features, such as the ability to embed new non-volatile memories—RRAM, phase change memory, and MRAM—right on the processor. The trouble is, those are really hard things to make at scale. So Applied has invented a pair of machines that boost throughput by more than an order of magnitude. It unveiled the machines on 9 July at Semicon West, in San Francisco.

Nvidia Chip Takes Deep Learning to the Extremes

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/tech-talk/semiconductors/processors/nvidia-chip-takes-deep-learning-to-the-extremes

Individual accelerator chips can be ganged together in a single module to tackle both the small jobs and the big ones without sacrificing efficiency

There’s no doubt that GPU-powerhouse Nvidia would like to have a solution for all size scales of AI—from massive data center jobs down to the always-on, low-power neural networks that listen for wakeup words in voice assistants.

Right now, that would take several different technologies, because none of them scale up or down particularly well. It’s clearly preferable to be able to deploy one technology rather than several. So, according to Nvidia chief scientist Bill Dallythe company has been seeking to answer the question: “Can you build something scalable… while still maintaining competitive performance-per-watt across the entire spectrum?” 

It looks like the answer is yes. Last month at the VLSI Symposia in Kyoto, Nvidia detailed a tiny test chip that can work on its own to do the low-end jobs or be linked tightly together with up to 36 of its kin in a single module to do deep learning’s heavy lifting. And it does it all while achieving roughly the same top-class performance.

The individual accelerator chip is designed to perform the execution side of deep learning rather than the training part. Engineers generally measure the performance of such “inferencing” chips in terms of how many operations they can do per joule of energy or millimeter of area. A single one of Nvidia’s prototype chips peaks at 4.01 tera-operations per second (1000 billion operations per second) and 1.29 TOPS per millimeter. Compared to prior prototypes from other groups using the same precision the single chip was at least 16 times as area efficient and 1.7 times as energy efficient. But linked together into a 36-chip system it reached 127.8 TOPS. That’s a 32-fold performance boost. (Admittedly, some of the efficiency comes from not having to handle higher-precision math, certain DRAM issues, and other forms of AI besides convolutional neural nets.)

Companies have mainly been tuning their technologies to work best for their particular niches. For example, Irvine, Calif.,-startup Syntiant uses analog processing in flash-memory to boost performance for very-low power, low-demand applications. While Google’s original tensor processing unit’s powers would be wasted on anything other than the data center’s high-performance, high-power environment.

With this research Nvidia is trying to demonstrate that one technology can operate well in all those situations. Or at least it can if the chips are linked together with Nvidia’s mesh network in a multichip module. These modules are essentially small printed circuit boards or slivers of silicon that hold multiple chips in a way that they can be treated as one large IC. They are becoming increasingly popular, because they allow systems composed of a couple of smaller chips—often called chiplets—instead of a single larger and more expensive chip.

“The multichip module option has a lot of advantages not just for future scalable [deep learning] accelerators but for building version of our products that have accelerators for different functions,” explains Dally.

Key to the Nvidia multichip module’s ability to bind together the new deep learning chips is an interchip network that uses a technology called ground-referenced signaling. As its name implies, GRS uses the difference between a voltage signal on a wire and a common ground to transfer data, while avoiding many of the known pitfalls of that approach. It can transmit 25 gigabits/s using a single wire, whereas most technologies would need a pair of wires to reach that speed. Using single wires boosts how much data you can stream off of each millimeter of the edge of the chip to a whopping terabit per second. What’s more, GRS’s power consumption is a mere picojoule per bit.

“It’s a technology that we developed to basically give the option of building multichip modules on an organic substrate, as opposed to on a silicon interposer, which is much more expensive technology,” says Dally.

The accelerator chip presented at VLSI is hardly the last word on AI from Nvidia. Dally says they’ve already completed a version that essentially doubles this chip’s TOPS/W. “We believe we can do better than that,” he says. His team aspires to find inferencing accelerating techniques that blow past the VLSI prototype’s 9.09 TOPS/W and reaches 200 TOPS/W while still being scalable.

DARPA’S $1.5-Billion Remake of U.S. Electronics: Progress Report

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/tech-talk/semiconductors/devices/darpas-15billion-remake-of-us-electronics-progress-report

Agency is adding security and AI design to a mix meant to boost U.S. industry

About a year ago, the U.S. Defense Advanced Research Projects Agency pulled back the covers on its five-year, $1.5-billion scheme to remake the U.S. electronics industry. The Electronics Resurgence Initiative included efforts in “aggressive specialization” for chip architectures, systems that are smart enough to reconfigure themselves for whatever data you throw at them, open-source hardware, 24-hour push-button system design, and carbon-nanotube-enabled 3D chip manufacturing, among other cool things. As always with DARPA, this is high-risk research; but if even half of it works out, it could change the nature not just of what kinds of systems are designed but also of who makes them and how they’re made.

On 18 June, IEEE Spectrum spoke with IEEE Fellow Mark Rosker, the new director of the Microsystems Technology Office, which is leading ERI at DARPA. Rosker talked about what’s happened in the ERI programs, what new components have been added, and what to expect from the 2nd ERI Summit. That event will be held 15-17 July in Detroit, Mich., and headlined by the CEOs of AMD, GlobalFoundries, and Qualcomm.

Mark Rosker on:

IEEE Spectrum: How is the Electronics Resurgence Initiative going?

Mark Rosker: It’s a really good question. And I guess that is the question that is the underpinning of the second summit that we’re going to be having, I guess, about a month from now. I think it’s going extremely well. What we’re doing now is moving closer towards DARPA’s more traditional mode of operation, in which we have identified specific areas that we think are really game-changing technologies that we’re trying to go after, and have specific programs that address each of those areas. At the same time, I’m constantly on the lookout for new projects, new programs, that will be disruptive and be within the charter of the Electronics Resurgence Initiative. So to a degree, that feels very comfortable to us, but in no way is that to say it’s incremental. It’s just how we do business.

IEEE Spectrum: What was the advantage to making a concerted push last year?

Mark Rosker: Running that many new-program starts at the same time probably is not the most efficient thing for us. By probably, I mean it isn’t. But in terms of its value in capturing the community, in capturing attention, in getting the people who traditionally have not been that interested in participating in government research, to pay attention, I think it had great value. I think that where we are now is: We have their attention. And so, it’s probably more important to regain that efficiency.

IEEE Spectrum: Can you give any updates on the progress in some of the key programs that started ERI off last year? Some of them had pretty amazing goals, such as seeking push-button 24-hour system design and making 90-nanometer foundries competitive with 7-nm ones.

Mark Rosker: A lot of the discussion that will be held in Detroit will be talking about some of the details of the specifics of what each of the performers have done. And I don’t want to get too far ahead and make some generalizations about how we’re doing in that area.

IEEE Spectrum: ERI’s programs were centered on three main pillars: design, architecture, and materials & integration. Has that evolved any now that there are new sub-programs in play?

Mark Rosker: At the summit, I’ll probably be talking about how, going forward, ERI will be divided into four different areas. The first area [will focus on] new materials and devices that go beyond the materials and device people traditionally had to use. Largely, we’re talking about silicon in that case. The second area is a very familiar theme that [former ERI director, now special assistant to director at DARPA] Bill Chappell talked a lot about: specialized functions circuits that are really focused and optimized to do specific tasks.  The third area is really tools that help you organize those specialized functions, and also enable you to incorporate security without necessarily being an expert at security. And then lastly, is heterogeneous integration: How do you tie these new specialized functions together.

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IEEE Spectrum: Heterogeneous integration, particularly through chiplets, is something that’s being actively explored and debated now by industry. Is there a back-and-forth between this program and that debate?

Mark Rosker: Yeah. I really do believe that in 10 years or in 20 years, this period of electronics, more than anything else, may be associated with heterogeneous integration. Really, it’s just the physical manifestation of everything we’ve been talking about. So what you’re asking is, what are the standards and processes that are going to allow this to take place on a global scale. The CHIPS program [Common Heterogeneous Integration and IP Reuse Strategies] certainly is an example of trying to create such standards, and push a community towards adopting that because there are mutual gains to be had if everybody designs in ways that allow reuse and compatibility.

My own opinion is that DARPA will not be able to drive that standards formation, certainly not in the commercial world. But what we can do is encourage the creation of those standards by the larger community by showing that, in certain cases and in certain domains, there are really large advantages to having those commercial standards. 

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IEEE Spectrum: What’s the roadmap for ERI going forward?

Mark Rosker: We started with a very large investment, we pushed a bunch of ideas out to the community, and we got a great reaction. We’re now sort of in year two, which is a really good time to take stock. We have a commitment to maintain at least five years in this process, and I probably shouldn’t speculate about what happens after five years. In any case, if we’re going to make midcourse changes, if we’re going to cover new areas that maybe we might have missed that we should have covered, now is a good time to be having that discussion and think about what those things should be. For example, in our second year, we had an increased focus on security, as well as on strengthening the manufacturing options that are available for specialized functions, like photonics or RF.

IEEE Spectrum: You began several new programs some months after the official launch, could you talk about those a bit?

Mark Rosker: At the launch in July, we had a day of workshops. And from those workshops, we took some of that community feedback and created what we call our Phase Two of programs. It was six additional programs that we’ve announced since November. Those haven’t kicked off yet, but they have been announced. There are six new efforts that are categorized around security, as well as a defense applications initiative and some manufacturing initiatives.

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IEEE Spectrum: Can you walk us through some of those new ones?

Mark Rosker: I can certainly tell you about what the program goals are.

I don’t think there’s any particular point to the order here. But first program is one called PIPES, which stands for Photonics in the Package for Extreme Scalability. And what this is really about is very-high-bandwidth optical signaling for digital interconnects. Photonic interconnects are something that everyone understands, but we’re really talking about driving very high bandwidth photonics all the way down to the package level.

IEEE Spectrum: Currently it stops at the rack level, right?

Mark Rosker: Exactly. Exactly. So, this would be useful for achieving sensationally high transfer rates all the way to the package.

[For some of the reasons why that hasn’t yet been achieved commercially, see “Silicon Photonics Stumbles at the Last Meter,” IEEE Spectrum, September 2018.]

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IEEE Spectrum: What’s next?

Mark Rosker: So the second program is called T-MUSIC, which stands for Technologies for Mixed-mode Ultra Scaled Integrated Circuits. [Hesitates.] I always have to check, because once you come up with the acronym no one ever remembers what it stands for. This is a program that is really focused on trying to develop very integrated and very broadband RF electronics. It’s combining silicon CMOS with silicon germanium technologies to get to next-generation mixed mode devices. These are things that could probably be up to the terahertz in terms of performance. Clearly, this is very highly relevant to the Department of Defense. The DOD typically is asking for extremely high performance even by commercial standards. But what it also offers is a route to onshore manufacturing. That’s very important in this particular program.

The third program in this list is the program called GAPS, which stands for Guaranteed Architecture for Physical Security. Again, this is getting back to the physical security part of the problem. Really what you’re talking about doing here is taking architectures that can be provably separated and provably shown to be secure. So it’s hardware components and interfaces, co-designed tools, and integration of the tools into systems that can be validated.

IEEE Spectrum: I’m going to need a little unpacking for that. What do you mean provably separate, provably secure? I’m not sure what’s being separated from what.

Mark Rosker: So to explain this, I want you to imagine that you have multiple tasks that you would like to do and that you want to ensure that one task does not talk to another task or that someone who is supposed to be getting information from one task doesn’t receive information that’s related to the other task. Ultimately, these could be things that could be at a different level of security from each other, or simply they may be—in the commercial world—they may be simply tasks that you want to make sure are kept separate. That is a significant problem in the DOD and government space.

IEEE Spectrum: And this is at the level of computer architecture?

Mark Rosker: Yup.

IEEE Spectrum: Is that what you’re talking about? This sounds a little bit like a response to Spectre and Meltdown in a way—information bleeding from one process to another due to an architecture issue.

Mark Rosker: I think that is certainly within the scope of the kinds of things that we’re interested in looking at.

The fourth program is called DRBE. We got a little bit creative with the acronymship, it’s Digital RF Battlefield Emulator. This is really quite interesting, because we’re using a problem that is of interest to the Department of Defense to serve as something that drives high performance computing in a larger way: high fidelity emulation of RF environments. If you were, for example, in downtown Chicago, and you had a large number of emitters around you—cell phone towers, just all the things that you’ll find in a city—trying to understand how that RF environment works is an immense computational problem.

IEEE Spectrum: Obviously, since you’re working on it I think I know the answer to this, but that’s not something that AT&T or Verizon can currently do? I mean, they can’t just stand in the space and get a complete picture of the RF environment?

Mark Rosker: Actually, it’s not anything that anyone can do. It depends on the level of fidelity at which you’re trying to simulate, of course. You can do an emulation of a system with a spreadsheet. But if you ask for a complex model that models what’s going on with a large number of emitters and a large number of what’s called multipaths, the problem grows geometrically. If I take a very small number—say, 10—it’s easy to do that. But if I take a very large number like the number of people in an urban environment, not really. No one can do that.

I’m being glib here because I’m saying number of people or number of emitters, but I also have to worry about the number of paths. It’s a multipath problem. And so that problem becomes very—it becomes intractable, actually.

IEEE Spectrum: What are some other new programs?

Mark Rosker: These are very new. One is called Real-Time Machine Learning, RTML. It probably sounds like what it is. It’s trying to reduce the design costs of developing AI or machine learning by developing ways to automatically generate the chip designs for machine learning. Really, I guess what you would say is that RTML is about making a machine learning compiler. If you could do that, it would be enormously important in terms of reducing the cost of building—I guess you could call it—a machine learning processor.

IEEE Spectrum: And is this aimed at the inferencing or training chips?

Mark Rosker: The training kind. This is basically the tensor processor and Pytorches of the world.

IEEE Spectrum: The ERI already has a hardware compiler component through the IDEA program right? 

Mark Rosker: Right, but there is no machine learning compiler that exists. It’s a completely separate problem. So this would be a first of its kind. The hardware compiler technology under development through POSH and IDEA, those programs are more traditional Von Neumann-type generalized processing.

IEEE Spectrum: There any other programs you want to talk about?

Mark Rosker: There’s one more that I haven’t mentioned and we call it AISS, Automatic Implementation of Secure Silicon. And this is a design program. It is run by [DARPA program manager] Serge Leef, and, basically, what it is about is creating an augmented chip design flow that is consistent with security mechanisms.

IEEE Spectrum: How does this differ from the other automated design programs that you’re already working on through POSH and IDEA?

Mark Rosker: POSH and IDEA are really about trying to deal with complexity. This is about secure silicon. How do you make a design which provides a way of evaluating and making sure you have achieved some security metric?

IEEE Spectrum: Security is always a moving target. What sort of things are going to have to be guarded against, by design? Or have you decided what those things are?

Mark Rosker: You’re right; in the security space you have to define the problem. AISS is specifically dealing with four threat vectors: side channel attacks, Trojan insertion, reverse engineering, and supply chain attacks such as cloning and counterfeiting.

IEEE Spectrum: Sort of like the GAPS program, but with automated design?

Mark Rosker: Yes. It is in that space between the two.

IEEE Spectrum: What’s your ideal outcome from the symposium in July?

Mark Rosker: I think, for us, the summit is all about engagement with the larger community. I think we have been very successful in the first year to attract the attention of a number of companies, ones we call non-traditional performers, [by which we mean] people who have not traditionally answered our call for responding to new ideas.

What I think we want to do moving forward is to couple better with those people and those communities and some of the more traditional performers that we have who work on problems.

But, again, we, at DARPA are always mindful that we’re a part of the Department of Defense. Ultimately, those improvements and capabilities that we develop, we want to see realized in applications that are important and disruptive for the Department of Defense.

So the ideal outcome is engagement. Not just between us and different communities, but between traditional and non-traditional performer communities. Having them together and talking to each other. And, hopefully, working with each other in ERI as we move forward.

IEEE Spectrum: Any fiscal year 2019 budget information you can share for ERI?

Mark Rosker: Well, I don’t think we announced the budget to the dollar. We committed to at least $1.5 billion over 5 years, and we are absolutely going to deliver on that.

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