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	<title>CXL 3.0 &#8211; Noise</title>
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		<title>XCENA MX1 RISC-V Computational Memory in CXL 3.0</title>
		<link>https://noise.getoto.net/2025/08/24/xcena-mx1-risc-v-computational-memory-in-cxl-3-0/</link>
		
		<dc:creator><![CDATA[Cliff Robinson]]></dc:creator>
		<pubDate>Sun, 24 Aug 2025 15:22:58 +0000</pubDate>
				<category><![CDATA[CXL]]></category>
		<category><![CDATA[CXL 3.0]]></category>
		<category><![CDATA[Other Components]]></category>
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					<description><![CDATA[We saw the XCENA MX1S and MX1P that will soon bring "1000s" of RISC-V cores to PCIe Gen6 and CXL 3 servers and memory pools
The post XCENA MX1 RISC-V Computational Memory in CXL 3.0 appeared first on ServeTheHome.
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		<title>XConn Tech Shows off New PCIe Gen6 and CXL 3 Switch Chips at FMS 2025</title>
		<link>https://noise.getoto.net/2025/08/24/xconn-tech-shows-off-new-pcie-gen6-and-cxl-3-switch-chips-at-fms-2025/</link>
		
		<dc:creator><![CDATA[Cliff Robinson]]></dc:creator>
		<pubDate>Sun, 24 Aug 2025 02:13:02 +0000</pubDate>
				<category><![CDATA[CXL]]></category>
		<category><![CDATA[CXL 3.0]]></category>
		<category><![CDATA[Other Components]]></category>
		<category><![CDATA[PCIe Gen6]]></category>
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					<description><![CDATA[At FMS 2025, we saw the new XConn Tech PCIe Gen6/ CXL 3 era switch chip running a live demo on the show floor
The post XConn Tech Shows off New PCIe Gen6 and CXL 3 Switch Chips at FMS 2025 appeared first on ServeTheHome.
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		<title>CXL 3.1 Specification Aims for Big Topologies</title>
		<link>https://noise.getoto.net/2023/12/02/cxl-3-1-specification-aims-for-big-topologies/</link>
		
		<dc:creator><![CDATA[Patrick Kennedy]]></dc:creator>
		<pubDate>Fri, 01 Dec 2023 22:51:00 +0000</pubDate>
				<category><![CDATA[compute express link]]></category>
		<category><![CDATA[CXL]]></category>
		<category><![CDATA[CXL 3.0]]></category>
		<category><![CDATA[CXL 3.1]]></category>
		<category><![CDATA[server]]></category>
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					<description><![CDATA[The updated CXL 3.1 specification adds new features around the fabric, security, and memory devices to aid in building larger topologies
The post CXL 3.1 Specification Aims for Big Topologies appeared first on ServeTheHome.
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