Tag Archives: Semiconductors/Materials

White paper on flame retardant epoxies and silicones

Post Syndicated from IEEE Spectrum Recent Content full text original https://spectrum.ieee.org/whitepaper/white-paper-on-flame-retardant-epoxies-and-silicones

Flame retardant epoxies

Epoxies and silicones used in aircraft applications must maintain their primary role as adhesives or coatings while exhibiting resistance to heat and flame in accordance with government and industry specifications. Master Bond’s flame-retardant systems comply with specifications for flame resistance and reduction of smoke density and toxic emissions.

Atoms-Thick Transistors Get Faster Using Less Power

Post Syndicated from Prachi Patel original https://spectrum.ieee.org/tech-talk/semiconductors/materials/atomsthick-transistors-get-faster-using-less-power

For post-silicon electronics, engineers have been doubling down on research aimed at making transistors from atoms-thick two-dimensional materials. The most famous one is graphene, but experts believe that 2D semiconductors such as molybdenum disulfide and tungsten disulfide might be better suited for the job. Graphene lacks a bandgap, the property that makes a material a semiconductor.

Now, by combining graphene and MoS2, researchers have made a transistor that operates at half the voltage and has a higher current density than any state-of-the-art 2D transistor previously under development. This should slash the power consumption of integrated circuits based on these 2D devices.

“We were able to fully explore the untapped potential of 2D materials to make a transistor that shows better performance in terms of energy consumption and switching speed,” says Huamin Li, the electrical engineering professor at the University of Buffalo who presented the device at the IEEE International Electron Devices Meeting (IEDM).

Interestingly, the device takes advantage of graphene’s lack of a bandgap. In a transistor, a voltage at the gate electrode injects charge carriers into the channel region to create a conductive path between the source and drain electrodes. Conventional silicon transistors and 2D MoS2 transistors take advantage of the emission of high-energy “hot” electrons from the source. This places a fundamental limit of 60 millivolts for each ten-fold increase in the drain current (60 mV/decade).

But graphene, with no bandgap, acts as a “cold” electron source, Li says. That means less energy is required to send electrons out across the channel region to the drain electrode. The result: The device current can be switched on and off more rapidly.

Using this unique mechanism we were able to break the fundamental limit of switching,” Li says. The group’s 1-nanometer-thick transistor needs only 29 mV to achieve that 10-fold change in device current. “We use less voltage to switch the device and control more current, so our transistor is much more energy efficient.”

Nanosilica Filled Optically Clear Epoxy Adhesive

Post Syndicated from Jane Trager original https://spectrum.ieee.org/semiconductors/materials/nanosilica-filled-optically-clear-epoxy-adhesive

Master Bond EP30NS is a two component epoxy system with moderate viscosity and good flow. It contains a nanosilica filler which lends to its specific property profile by providing a much higher abrasion resistance than a typical epoxy, and much lower linear shrinkage upon cure. EP30NS passes ASTM E595 for NASA low outgassing.

To obtain optical properties, cure overnight at room temperature, followed by 2-3 hours at 150-200°F. The epoxy has a moderate mixed viscosity ranging from 25,000 to 45,000 cps. It is optically clear, with a refractive index of 1.56. EP30NS has been independently tested per ASTM D4060-14 for abrasion resistance for 1,000 cycles and exhibited a loss of weight of only 18.3 mg. It is thus able to withstand exposure to scuffing, gouging, scraping, scratching and wear.

This system has excellent electrical insulation, making it well suited for small potting applications. It forms dimensionally stable, rigid bonds. It bonds well to metals, glass, ceramics, composites, rubbers, and plastics. It is chemically resistant to water, fuels, oils, acids and solvents.  The service temperature range is from -60°F to +300°F. This system is recommended for high tech applications in the aerospace, electronic, optical, opto-electronic and specialty OEM industries. It is available in both standard packaging and specialty gun dispenser packaging.

For more information on EP30NS and to request a technical datasheet please visit https://www.masterbond.com/tds/ep30ns.

Can Two-dimensional Semiconductors Created Using Liquid Metals Forestall Moore’s Law’s Demise?

Post Syndicated from John Boyd original https://spectrum.ieee.org/nanoclast/semiconductors/materials/twodimensional-semiconductors-created-using-liquid-metals-the-answer-to-moores-law-demise

As the semiconductor industry witnesses the winding down of the expectation that the number of transistors that can be shoehorned into silicon microchips will double every couple of years, researchers are coming up with new ways to keep the effect of Moore’s Law rolling along. One such method with exciting prospects employs liquid metals to produce two-dimensional semiconducting materials with atomic-scale thickness. This enables the creation of a transistor channel between source and drain that is almost an order of magnitude thinner than those employed in silicon transistors. In addition, they possess intriguing properties such as a variety of band gaps and carrier concentrations, as well as unique transducing properties.

“The two-dimensional confinement of free charge-carriers—namely electrons and holes—in these materials provides a pathway to move along with reduced charge scattering,” says Kourosh Kalantar-Zadeh, a professor of engineering at the University of New South Wales, Australia. “This means extremely small resistance. In theory, they can also switch very fast and switch off to absolute zero resistance during non-operational states due to their very thin nature.”

But several barriers make it difficult to use these new materials as ultra-thin semiconductors for integrated circuits. Besides imperfections and defects arising in their production that can inhibit electron flow, a major issue to date has been the grain barriers that exist across their planes when they’re produced using conventional deposition methods.

To overcome this problem, Kalantar-Zadeh’s research group has developed a new deposition method to produce one of the most promising ultra-thin semiconductor materials, molybdenum disulfide (MoS2), without grain barriers.

“We use the unique capability of gallium metal, which, unlike mercury for instance, is much less hazardous and has the amazing quality of turning to liquid at just 29.8 0C,” says Yifang Wang, a member of Kalantar-Zadeh’s group and first author of a paper published on the research in Advanced Functional Materials this October. “Indeed, it turns to liquid when held in the palm of your hand.”

And because gallium is a melted metal, she says its surface is atomically smooth, yet like conventional metals, its surface provides a large number of free electrons to facilitate chemical reactions, which is important for the new method of deposition.

Kalantar-Zadeh explains the method as follows. The sources of molybdenum and sulfur are brought near to the surface of the liquid gallium. This causes a chemical reaction that forms molybdenum sulfur bonds that in turn create MoS2. The newly formed material is grown on the atomically smooth surface of the gallium like a skin, so it is naturally formed and grain free. This process takes place in an aqueous solution and requires annealing to remove hydration. Distance-dependent surface forces such as electrostatic or dipolar forces are then used to remove the semiconductor skin from the gallium liquid and to transfer it to a substrate ready for turning into transistor elements. Such forces do not exist on the surface of liquid metals, and so the synthesized MoS2 does not adhere to their surfaces.

“Unlike conventional chips that require a silicon substrate, the molybdenum disulfide skin can be deposited onto almost anything non-metallic: glass, a polymer,” says Kalantar-Zadeh. “You can roll it out or print it out anywhere you like. If you want something flexible, if you want to bend it, for instance, you can deposit it on a suitable polymer substrate to produce flexible electronics.”

And because the material is thinner than silicon, a number of layers can be added as desired, while standard chip packaging can also be used.

Having demonstrated the deposition method’s feasibility, the researchers are now working to streamline it so that it can be transferred from the lab to commercial fabs—something Kalantar-Zadeh estimates can be accomplished in the next several years. 

The researchers are also planning to extend the method to create other two-dimensional semiconducting, dielectric, and conducting materials such as gallium arsenide, gallium sulfide, and indium tin oxide. 

Applied Materials Says New Tool Breaks Chip Resistance Bottleneck

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/nanoclast/semiconductors/materials/applied-materials-says-new-tool-breaks-chip-resistance-bottleneck

The regular scaling down in the size of transistors has always had a similar scaling down in the size of the vertical metal contacts that bridge the devices themselves to the wiring that links them up to form logic gates.

But in the last few generations the resistance of those tungsten contacts has become a drag on performance, and chip makers had been eyeing moves to alternative materials for future generations. Chip equipment supplier Applied Materials says it’s come up with a machine that reverses this resistance problem, boosting the performance of today’s chips and allowing fabs to continue using tungsten into the future.

For devices on today’s most advanced chips “resistance is your key issue,” says Zhebo Chen, global product manager. “With the transistor you’ve taken an economy car and turned it into a race car, but if the roads are congested it doesn’t matter.”

The heart of the problem is that in the existing manufacturing process, tungsten contacts must be clad in a layer of titanium nitride. The process involves first forming a hole in a layer of dielectric to contact the transistor, then adding a layer of titanium nitride to line that hole and the surface of the dielectric. The next step uses a process called chemical vapor deposition to put tungsten on all the surfaces at once, growing from the nitride layer inwards within the holes until the hole is filled. Finally, the surface layer of tungsten is removed, leaving just the nitride-clad contacts.

The purpose of the nitride is two-fold. First, it helps the tungsten stick to the walls as the contact grows, preventing flaking. Second, it blocks fluorine used in the growth process from fouling the chip.

The problem is that even as the diameter of the contact has been shrunk down, the thickness of the cladding has not. In 7-nanometer chips today, contacts are only 20 nanometers wide, and only 25 percent of their volume is tungsten, explains Chen. The rest is cladding.

In July, Applied Materials released a machine that can make tungsten contacts with no cladding at all, reducing resistance by 40 percent. This “selective gapfill process” deposits tungsten from the bottom of the contact hole up instead of on all the surfaces at once. Because it uses a different chemistry than the previous process, there’s no need for a liner’s adhesion enhancement nor its fluorine-blocking ability. However, the process does need to be accomplished completely in a vacuum, so the company built it around a sealed system capable of moving wafers through multiple process steps without exposing them to air.

Although the new machine, called the Endura Volta Selective Tungsten CVD system, was introduced in July, Chen says it’s already being used in high-volume manufacturing by leading manufacturers.

“There’s more than 100 kilometers of tungsten contact on a [300-millimeter] wafer,” says Chen. “Doing this right in high-volume manufacturing is exceedingly difficult.”

Fractal Topological Insulators Are All Edge

Post Syndicated from Charles Q. Choi original https://spectrum.ieee.org/nanoclast/semiconductors/materials/fractal-topological

In novel materials known as topological insulators, electricity or light can flow around corners and defects with virtually no losses. All topological insulators produced so far are comprised of an insulating bulk and perfectly conductive edges. Now scientists have found—at least in theory—that fractal topological insulators could possibly be made up only of edges, with no bulk at all.

Topology is the branch of mathematics that explores what aspects of shapes can survive deformation. For example, an object shaped like a doughnut can get deformed into the shape of a mug, with the doughnut’s hole forming the hole in the cup’s handle, but it could not get pushed or pulled into a shape that lacked a hole without ripping the item apart.

Employing insights from topology, researchers developed the first electronic topological insulators in 2007. Electrons zipping along the edges or surfaces of these materials strongly resist any disturbances that might hamper their flow, much as a doughnut might resist any change that would remove its hole.

U.S. and Japan Seeking to Break China’s Grip on Rare Earths Production

Post Syndicated from John Boyd original https://spectrum.ieee.org/tech-talk/semiconductors/materials/us-and-japan-seeking-to-break-chinas-grip-on-rare-earths

You may not have realized it, but praseodymium, terbium, and gadolinium are as important to your work as the soldering iron, multimeter, and oscilloscope. Respectively, these rare earth elements (REEs) help make possible lasers and certain magnets, fluorescent lamps and sonar systems, computer memories and X-ray tubes. 

There are seventeen REEs, and most of them play a special role in 21st Century living—several pounds of these compounds, for instance, are used in batteries for electric and hybrid vehicles. But the industry producing them is overshadowed by the fact it has become a monopoly of China, which is not shy about threatening to restrict REE exports when aggrieved. 

Ironically, most REEs are not particularly rare. Rather, they are seldom found in concentrated amounts large enough to make them readily profitable to extract and refine. That wasn’t always the case. The Mountain Pass mine in California’s Mojave Desert was the world’s largest supplier of certain REEs from the 1950s to 1990s, supplying the needs of color TV makers and electronics manufacturers that supplied the U.S. defense industry during the Cold War. With the end of that war and the issuing of stringent government environmental regulations, the mine went out of business in 2002.

Meanwhile, China—a rich source of REEs—began to seriously develop technology for extracting, separating, smelting, and processing REEs in the mid-1970s. Less regulated and supported by the government, the country became a major REE exporter in the 1980s, going on to account for an astonishing 97 percent market share of all rare earth mineral production in 2010. Though China’s share has since decreased to around 70–80 percent, it has become the world’s largest consumer of REEs, in keeping with its spectacular growth in high tech manufacturing. 

In a paper reviewing China’s REE policies from 1975­­­–2018 published in Mineral Economics this January, the authors note that the Chinese government, in efforts to manage resources, reduce pollution and encourage the country’s industrial growth, asserted control over the REE industry in the 1990s. Export restrictions and production quotas were introduced and REE prices soared. 

When the rest of the industrialized world woke up to their dependency, China reversed its strategy on REE prices, “keeping them low and making it difficult [for other countries] to compete,” says Kristin Vekasi of the University of Maine, interviewed last summer by the National Bureau of Asian Research, a think tank advising the U.S. government. Not only that, but ten years ago China used administrative regulations to evade breaking World Trade Organization rules when it halted exports of REEs to Japan, after a dispute erupted over islands in the South China Sea both countries claim. And last summer during the trade tariff dispute between China and the U.S., China’s official government newspaper People’s Daily raised the possibility of using REE exports as a way to pressure the U.S., while Chinese President Xi Jinping at the time notably called REES “an important strategic resource.”

The Japanese were quick to respond to the threat of blocked exports. The state and private sector collaborated to encourage recycling and diversification of REE supplies. “By late 2017, Japan was importing around 30% of its rare earth from Asian countries other than China,” notes Vekasi. 

What’s more, in 2013 Japanese researchers discovered rich supplies of REEs in deep sea mud within Japan’s exclusive economic zone in the Pacific Ocean, 6,000 meters below the surface. Yasuhiro Kato, at the School of Engineering, University of Tokyo, who led the search, told IEEE Spectrum they estimate well over one million tons of certain REEs are distributed in the ocean floor sediment in the most promising area searched. 

Kato adds that a government program is now underway to explore and retrieve the REEs. “For certain industrially important REEs such as yttrium and europium, more than three to ten times Japan’s annual demand can be supplied from this [single] area,” says Kato. “Even if a smaller amount of REE-rich mud can be developed, the project will significantly contribute to reducing Japan’s imports of REEs.”

As for the U.S. according to a 2016 report from the Department of Commerce, the country was “once self-reliant…for REEs, but has become nearly fully reliant on REE imports…primarily from China.” The report goes on to say that the Chinese near-monopoly and unilateral action over prices “has raised concerns with numerous U.S. Government institutions including Congress and the U.S. Department. of Defense.”

Subsequently, last November, the U.S. and Australia agreed to work together on securing REE resources and to support private industries in achieving that goal, and this January the U.S. signed a similar agreement with Canada.

So encouraged, a Chicago-NY financial group formed MP Materials to acquire the Mountain Pass mine in 2017 and has restarted operations using new equipment. Today, the company is producing 15 percent of the global supply of REEs—currently sent to China for processing—and plans to reopen its own processing facilities in 2022.

In research funded by the Department of Energy, Lawrence Livermore National Laboratory (LLNL), Pennsylvania University, and Idaho National Laboratory are jointly developing a new protean-based environment-friendly process to extract and purify REEs from low-grade sources, which otherwise require toxic chemicals to process. The bio-sourced compound known as Lanmodulin (LanM) “has an unprecedented appetite and selectivity for REEs,” Gauthier Deblonde, a staff scientist at LLNL, tells IEEE Spectrum. “And our collaboration has yielded a completely new and green process for REE extraction and purification.”

To date, the researchers have tested the process using electronic waste containing a broad range of impurities and now believe it will work with all 17 REEs. “Many alternative secondary sources containing REEs have remained untapped because there is no efficient method to extract them,” says Deblonde. “Our green LanM-based approach will open up various opportunities to produce or recycle REEs.”

Superhigh-voltage Gallium Oxide Transistors Could Transform Power Electronics

Post Syndicated from Prachi Patel original https://spectrum.ieee.org/tech-talk/semiconductors/materials/gallium-oxide-transistors-can-handle-over-8000-volts

A new gallium oxide transistor can withstand voltages of over 8,000 volts (V), the highest ever reported for a device of comparable size. The advance opens up exciting possibilities for compact, energy-efficient power electronics systems based on a technology that is only eight years old: the first gallium oxide transistors were reported in 2012.

“Those are extraordinary numbers compared to what’s reported,” says Uttam Singisetti, a professor of electrical engineering at the University of Buffalo who led the new device research published in IEEE Electron Device Letters. “Reaching 8kV in eight years is a big achievement.”

Graphene Solar Thermal Film Could Be a New Way to Harvest Renewable Energy

Post Syndicated from John Boyd original https://spectrum.ieee.org/energywise/semiconductors/materials/graphene-solar-heating-film-potential-new-renewable-energy-source

Researchers at the Center for Translational Atomaterials (CTAM) at Swinburne University of Technology in Melbourne, Australia, have developed a new graphene-based film that can absorb sunlight with an efficiency of over 90 percent, while simultaneously eliminating most IR thermal emission loss—the first time such a feat has been reported.

The result is an efficient solar heating metamaterial that can heat up rapidly to 83 degrees C (181 degrees F) in an open environment with minimal heat loss. Proposed applications for the film include thermal energy harvesting and storage, thermoelectricity generation, and seawater desalination.

Chicken Droppings Can Make Graphene More Catalytic

Post Syndicated from Charles Q. Choi original https://spectrum.ieee.org/nanoclast/semiconductors/materials/graphene-doping-catalyst-materials-research-news

Practically any kind of crap can boost graphene’s properties as a catalyst—even chicken droppings, say the authors of a new tongue-in-cheek study.

Graphene is often hailed as a wonder material—flexible, transparent, light, strong, and electrically and thermally conductive. Such qualities have led researchers worldwide to consider weaving these one-atom-thick sheets of carbon into advanced devices. Scientists have also explored graphene’s properties as a catalyst for the kinds of oxygen reduction reactions often used in fuel cells and the hydrogen evolution reactions used to split apart water molecules to generate hydrogen fuel.

To further enhance graphene’s catalytic properties, researchers have tried doping it with a variety of elements. Seemingly all such studies have claimed graphene’s catalytic abilities improved, regardless of whether the doping materials had contrasting properties with each other. This is “contrary to what any material scientist might expect,” says Martin Pumera, a materials scientist at the University of Chemistry and Technology in Prague.

First Blue LED Emission From a Perovskite

Post Syndicated from Jeff Hecht original https://spectrum.ieee.org/tech-talk/semiconductors/materials/first-blue-led-emission-perovskite-news

Researchers in California have extended the spectral range of perovskite light-emitting diodes into the blues. How did they do it? By cracking the mystery of why the optical and electronic properties of the materials change when current flows through them.

Painstaking measurements revealed that current-induced heating deformed cells in the semiconductor crystals. That observation enabled the team to make the first single-crystal perovskite diodes, says group leader Peidong Yang, a chemistry professor at the University of California at Berkeley. 

Coming Soon to a Processor Near You: Atom-Thick Transistors


Post Syndicated from Iuliana Radu original https://spectrum.ieee.org/semiconductors/materials/coming-soon-to-a-processor-near-you-atomthick-transistors

If there’s one thing about Moore’s Law that’s obvious to anyone, it’s that transistors have been made smaller and smaller as the years went on. Scientists and engineers have taken that trend to an almost absurd limit during the past decade, creating devices that are made of one-atom-thick layers of material.

The most famous of these materials is, of course, graphene, a hexagonal honeycomb-shaped sheet of carbon with outstanding conductivity for both heat and electricity, odd optical abilities, and incredible mechanical strength. But as a substance with which to make transistors, graphene hasn’t really delivered. With no natural bandgap—the property that makes a semiconductor a semiconductor—it’s just not built for the job.

Instead, scientists and engineers have been exploring the universe of transition metal dichalcogenides, which all have the chemical formula MX2. These are made up of one of more than a dozen transition metals (M) along with one of the three chalcogenides (X): sulfur, selenium, or tellurium. Tungsten disulfide, molybdenum diselenide, and a few others can be made in single-atom layers that (unlike graphene) are natural semiconductors. These materials offer the enticing prospect that we will be able to scale down transistors all the way to atom-thin components long after today’s silicon technology has run its course.

While this idea is really exciting, I and my colleagues at Imec believe 2D materials could actually show up much sooner, even while silicon still remains king. We’ve been developing a technology that could put 2D semiconductors to work in silicon chips, enhancing their abilities and simplifying their designs.

Devices made with 2D materials are worth all the scientific and engineering work we and other researchers around the world have put into them because they could eliminate one of the biggest problems with today’s transistors. The issue, the result of what are called short-channel effects, is a consequence of the continual shrinking of the transistor over the decades.

A metal-oxide semiconductor field-effect transistor (MOSFET), the type of device in all digital things, is made up of five basic parts: The source and drain electrodes; the channel region that connects them; the gate dielectric, which covers the channel on one or more sides; and the gate electrode, which contacts the dielectric. Applying a voltage at the gate relative to the source creates a layer of mobile charge carriers in the channel region that forms a conductive bridge between the source and drain, allowing current to flow.

But as the channel was made smaller and smaller, current would increasingly leak across it even when there was no voltage on the gate, wasting power. The change from the planar designs of the 20th century to the FinFET transistor structure used in today’s most advanced processors was an attempt to counter this important short-channel effect by making the channel region thinner and having the gate surround it on more sides. The resulting fin-shaped structure provides better electrostatic control. (The coming move to the nanosheet transistor is a furthering of this same idea. See “The Last Silicon Transistor,” IEEE Spectrum, August 2019.)

Certain 2D semiconductors could circumvent short-channel effects, we think, by replacing the silicon in the device channel. A 2D semiconductor provides a very thin channel region—as thin as a single atom if only one layer of semiconductor is used. With such a restricted pathway for current to flow, there is little opportunity for charge carriers to sneak across when the device is meant to be off. That means the transistor could continue to be shrunk down further with less worry about the consequences of short-channel effects.

These 2D materials are not only useful as semiconductors, though. Some, such as hexagonal boron nitride, can act as gate dielectrics, having a dielectric constant similar to that of silicon dioxide, which was routinely used for that job until about a decade ago. Add graphene in place of the transistor’s metal parts and you’ve got a combination of 2D materials that forms a complete transistor. Indeed, separate groups of researchers built such devices as far back as 2014. While these prototypes were much larger, you could imagine scaling them down to the size of just a few nanometers.

As amazing as an all-2D transistor that’s a fraction of the size of today’s devices might be, that won’t be the first implementation of 2D materials in electronic circuits. Instead, 2D materials will probably arrive in low-power circuits that have more relaxed performance requirements and area constraints.

The set of circuits we’re targeting at Imec are built in the so-called back-end-of-line. Chipmaking is divided into two parts: the front-end-of-line part consists of processes—many of them requiring high temperatures—that alter the silicon itself, such as implanting dopants to define the parts of a transistor. The back-end-of-line part builds the many layers of interconnects that link the transistors to form circuits and deliver power.

With traditional transistor scaling becoming more and more difficult, engineers have been looking for ways to add functionality to the interconnect layers. You can’t do this simply by using ordinary silicon processes because the heat involved would damage the devices and interconnects beneath them. So, many of these schemes rely on materials that can be made into devices at relatively low temperatures.

A specific advantage of using 2D semiconductors instead of some other candidates is the potential ability to build both p-type (carrying positive charges) and n-type (carrying electrons) devices, a necessity in CMOS logic. CMOS circuits are the backbone of today’s logic because, ideally, they consume power only when switching from one state to the other. In our preferred 2D semiconductor, we’ve demonstrated n-type transistors but not yet p-type. However, the physics underlying these materials strongly suggests we can get there through engineering the dielectrics and metals that contact the semiconductor.

Being able to produce both p– and n-type devices would allow the development of compact back-end logic circuits such as repeaters. Repeaters essentially relay data that must travel relatively far across a chip. Ordinarily, the transistors involved reside on the silicon, but that means signals must climb up the stack of interconnects until they reach a layer where they can travel part of the distance to their destination, then go back down to the silicon to be repeated and up again to the long-distance interconnect layer. It’s a bit like having to exit the highway and drive into the center of a crowded city to buy petrol before getting back on the highway.

A repeater up near the long-distance interconnect layer is more akin to a motorway petrol station. It saves the time it would take the signal to make the two-way vertical trip and also prevents the loss of power due to the resistance of the vertical interconnects. What’s more, moving the repeater to the interconnect layer saves space on the silicon for more logic.

Repeaters aren’t the only potential use. A 2D material could also be used to build other circuits, such as on-chip power-management systems, signal buffers, and memory selectors. One thing these circuits all have in common is that they don’t require the device to drive a lot of current, so one layer of 2D material would probably be sufficient.

Neither future supersmall 2D devices nor the less demanding back-end-of-line circuits will be possible without a fabrication process compatible with industry-standard 300-millimeter silicon wafers. So our team at Imec is working on just that, hoping to develop a process that will serve for all applications.

The first step is identifying the most promising 2D material and device architecture. We have therefore benchmarked a variety of 2D semiconductors and 2D FET architectures against an advanced silicon FinFET device.

Because researchers have the most experience with molybdenum disulfide (MoS2), experimental devices made using it have advanced furthest. Indeed, at the IEEE International Electron Device Meeting last December, Imec unveiled an MoS2 transistor with a channel just 30 nanometers across and source and drain contacts only 13 nm long. But after examining the possibilities, we’ve decided that MoS2 is not the answer. Instead, we concluded that among all the materials compatible with 300-mm silicon-wafer technology, tungsten disulfide (WS2) in the form of a stacked nanosheet device has the highest performance potential, meaning it can drive the most current. For less demanding, back-end-of-line applications, we also concluded that a FET architecture with a gate both below and above the semiconductor channel region works better than one with only a single gate.

We already knew one important thing about WS2 before we reached that conclusion: We can make a high-quality version of it on a 300-mm silicon wafer. We demonstrated that for the first time in 2018 by growing the material on a wafer using metal-organic chemical vapor deposition (MOCVD), a common process that grows crystals on a surface by means of a chemical reaction. The approach we took results in thickness control down to a single-molecule layer, or monolayer, over the full 300-mm wafer. The benefits of the MOCVD growth come, however, at the price of a high temperature—and recall that high temperatures are forbidden in back-end processes because they could damage the silicon devices below.

To get around this problem, we grow the WS2 on a separate wafer and then transfer it to the already partially fabricated silicon wafer. The Imec team developed a unique transfer process that allows a single layer of WS2—as thin as 0.7 nm—to be moved to a silicon target wafer with negligible degradation in the 2D material’s electrical properties.

The process starts by growing the WS2 on an oxide-covered silicon wafer. That’s then placed in contact with a specially prepared wafer. This wafer has a layer of material that melts away when illuminated by a laser. It also has a coating of adhesive. The adhesive side is pressed to the WS2-covered wafer, and the 2D material peels away from the growth wafer and sticks to the adhesive. Then the adhesive wafer with its 2D cargo is flipped over onto the target silicon wafer, which in a real chipmaking effort would already have transistors and several layers of interconnect on it. Next, a laser is shone through the wafer to break the bulk of it away, leaving only the adhesive and the WS2 atop the target wafer. The adhesive is removed with chemicals and plasma. What’s left is just the processed silicon with the WS2 attached to it, held in place by Van der Waals forces.

The process is complicated, but it works. There is, of course, room for improvement, most importantly in mitigating defects caused by unwanted particles on the wafer surface and in eliminating some defects that occur at the edges.

Once the 2D semiconductor has been deposited, building devices can begin. On that front there have been triumphs, but some major challenges remain.

Perhaps the most crucial issue to tackle is the creation of defects in the WS2. Imperfections profoundly degrade the performance of a 2D device. In ordinary silicon devices, charge can get caught in imperfections at the interface between the gate dielectric and the channel region. These can scatter electrons or holes near the interface as they try to move through the device, slowing things down. With 2D semiconductors the scattering problem is more pronounced because the interface is the channel.

Sulfur vacancies are the most common defects that affect device channel regions. Imec is investigating how different plasma treatments might make those vacancies less chemically reactive and therefore less prone to alter the transistor’s behavior. We also need to prevent more defects from forming after we’ve grown the monolayer. WS2 and other 2D materials are known to age quickly and degrade further if already defective. Oxygen attacking a sulfur vacancy can cause more vacancies nearby, making the defect area grow larger and larger. But we’ve found that storing the samples in an inert environment makes a difference in preventing that spread.

Defects in the semiconductor aren’t the only problems we’ve encountered trying to make 2D devices. Depositing insulating materials on top of the 2D surface to form the gate dielectric is a true challenge. WS2 and similar materials lack dangling bonds that would otherwise help fasten the dielectric to the surface.

Our team is currently exploring two routes that might help: One is atomic layer deposition (ALD) at a reduced growth temperature. In ALD, a gaseous molecule adsorbs to the semiconductor’s exposed surface to form a single layer. Then a second gas is added, reacting with the adsorbed first one to leave an atomically precise layer of material, such as the dielectric hafnium dioxide. Doing this at a reduced temperature increases the ability of the gas molecules to stick to the surface of the WS2 even when no chemical bonds are available.

The other option is to enhance ALD by using a very thin oxidized layer, such as silicon oxide, to help nucleate the growth of the ALD layer. A very thin layer of silicon is deposited by a physical deposition method such as sputtering or evaporation; it’s then oxidized before a regular ALD deposition of gate oxide is done. We’ve achieved particularly good results with evaporation.

A further challenge in making superior 2D devices is in choosing the right metals to use as source and drain contacts. Metals can alter the characteristics of the device, depending on their work function. That parameter, the minimum energy needed to extract an electron from the metal, can mean the difference between a contact that can easily inject electrons and one that can inject holes. So the Imec team has screened a variety of metals to put in contact with the WS2 nanosheet. We found that the highest on-current in an n-type device was obtained using a magnesium contact, but other metals such as nickel or tungsten work well. We’ll be searching for a different metal for future p-type devices.

Despite these challenges, we’ve been able to estimate the upper limits of device performance, and we’ve mapped out what roads to follow to get there.

As a benchmark, the Imec team used dual-gated devices like those we described earlier. We built them with small, naturally exfoliated flakes of WS2, which have fewer defects than wafer-scale semiconductors. For these lab-scale devices, we were able to measure electron mobility values up to a few hundred square centimeters per volt-second, which nearly matches crystalline silicon and is close to the theoretically predicted maximum for the 2D material. Because this excellent mobility can be found in natural material, we are confident that it should also be possible to get there with materials synthesized on 300-mm wafers, which currently reach just a few square centimeters per volt-second.

For some of the main challenges ahead in 2D semiconductor development, our team has a clear view of the solutions. We know, for example, how to grow and transfer the material onto a 300-mm target wafer; we’ve got an idea of how to integrate the crucial gate dielectric; and we’re on a path to boost the mobility of charge carriers in devices toward a level that could compare with silicon.

But, as we’ve laid out, there are still significant problems remaining. These will require an intensive engineering effort and an even better fundamental understanding of this new class of intriguing 2D materials. Solving these challenges will enable high-performance devices that are scaled down to atomic layers, but they might first bring new capabilities that need less demanding specifications even as we continue to scale down silicon.

This article appears in the February 2020 print issue as “Atom-Thick Transistors.”

About the Author

Iuliana Radu is program director at Imec, in Leuven, Belgium, where she leads the research center’s Beyond CMOs program and quantum computing activities.

Ferroelectric Semiconductors Could Mix Memory and Logic

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/nanoclast/semiconductors/materials/ferroelectric-semiconductors-could-mix-memory-and-logic

Engineers at Purdue University and at Georgia Tech have constructed the first devices from a new kind of two-dimensional material that combines memory-retaining properties and semiconductor properties. The engineers used a newly discovered ferroelectric semiconductor, alpha indium selenide, in two applications: as the basis of a type of transistor that stores memory as the amount of amplification it produces; and in a two-terminal device that could act as a component in future brain-inspired computers. The latter device was unveiled last month at the IEEE International Electron Devices Meeting in San Francisco.

Ferroelectric materials become polarized in an electric field and retain that polarization even after the field has been removed. Ferroelectric RAM cells in commercial memory chips use the former ability to store data in a capacitor-like structure. Recently, researchers have been trying to coax more tricks from these ferroelectric materials by bringing them into the transistor structure itself or by building other types of devices from them.

In particular, they’ve been embedding ferroelectric materials into a transistor’s gate dielectric, the thin layer that separates the electrode responsible for turning the transistor on and off from the channel through which current flows. Researchers have also been seeking a ferroelectric equivalent of the memristors, or resistive RAM, two-terminal devices that store data as resistance. Such devices, called ferroelectric tunnel junctions, are particularly attractive because they could be made into a very dense memory configuration called a cross-bar array. Many researchers working on neuromorphic- and low-power AI chips use memristors to act as the neural synapses in their networks. But so far, ferroelectric tunnel junction memories have been a problem.

“It’s very difficult to do,” says IEEE Fellow Peide Ye, who led the research at Purdue University. Because traditional ferroelectric materials are insulators, when the device is scaled down, there’s too little current passing through, explains Ye. When researchers try to solve that problem by making the ferroelectric layer very thin, the layer loses its ferroelectric properties.  

Instead, Ye’s group sought to solve the conductance problem by using a new ferroelectric material—alpha indium selenide— that acts as a semiconductor instead of an insulator. Under the influence of an electric field, the molecule undergoes a structural change that holds the polarization. Even better, the material is ferroelectric even as a single-molecule layer that is only about a nanometer thick. “This material is very unique,” says Ye.

Ye’s group made both transistors and memristor-like devices using the semiconductor. The memristor-like device, which they called a ferroelectric-semiconductor junction (FSJ), is just the semiconductor sandwiched between two conductors. This simple configuration could be formed into a dense cross-bar array and potentially shrunk down so that each device is only about 10 nanometers across, says Ye.

Proving the ability to scale the device down is the next goal for the research, along with characterizing how quickly the devices can switch, explains Ye. Further on, his team will look at applications for the FSJ in neuromorphic chips, where researchers have been trying a variety of new devices in the search for the perfect artificial neural synapse.

Custom Computer Makes Inverse Lithography Technology Practical for First Time

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/nanoclast/semiconductors/materials/custom-computer-makes-inverse-lithography-practical-for-first-time

Silicon Valley-based D2S revealed last week that it had solved the last problem in a nascent technique called inverse lithography technology, or ILT. The breakthrough could speed the process of making chips and allow semiconductor fabs to produce more advanced chips without upgrading equipment. The solution, a custom-built computer system, reduces the amount of time needed for a critical step from several weeks to a single day.

In most of the photolithography used to make today’s microchips, light with a wavelength of 193-nanometers is shown through lenses and a patterned photomask, so that the pattern is shrunk down and projected onto the silicon wafer where it defines device and circuit features. (The most modern chip making technology, extreme ultraviolet lithography, works a bit differently. But, only a few chipmakers have these tools.)

Solve Your Thin Film Challenges in High-Volume Compound Semi Manufacturing

Post Syndicated from IEEE Spectrum Recent Content full text original https://spectrum.ieee.org/whitepaper/addressing-thin-film-challenges-in-highvolume-compound-semiconductor-manufacturing-a-360degree-solution

In this white paper, you’ll learn how investing in a robust, reliable thin film deposition solution will better position compound semi manufacturers for high-volume production.

Scaling into high-volume production for compound semiconductor manufacturing does not just involve achieving a higher throughput and factory output. Compound semi manufacturers need to invest in a robust, reliable thin film deposition solution that is configured for high throughput and excellent precision. In this white paper, you’ll learn how a flexible configuration with the right hardware, software and partner support will lead to a better production process and performance and a lower cost of ownership.

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