“Ironically, one of the safest places to be right now is in a cleanroom,” points out Thomas Sonderman, president of SkyWater Technology, in Bloomington, Minn.
Like every business, semiconductor foundries like SkyWater and GlobalFoundries have had to make some pretty radical changes to their operations in order to keep their workers safe and comply with new government mandates, but there are some unique problems to running a 24/7 chip-making operation.
GlobalFoundries’ COVID-19 plan is basically an evolution of its response to a previous coronavirus outbreak, the 2002-3 SARS pandemic. When the company acquired Singapore-based Chartered Semiconductor in 2010, it inherited a set of fabs that had managed to produce chips through the worst of that outbreak. (According to the World Health Organization, Singapore suffered 238 SARS cases and 33 deaths.)
“During that period we established business policies, protocols, and health and safety measures to protect our team while maintaining operations,” says Ronald Sampson, GlobalFoundries’ senior vice president and general manager of U.S. fab operations. “That was a successful protocol that served as the basis for this current pandemic that we’re experiencing together now. Since that time we’ve implemented it worldwide and of course in our three U.S. factories.”
At Fab 8 in Malta, N.Y., GlobalFoundries’ most advanced 300-mm CMOS facility, that translates into a host of procedures. Some of them are common, such as working from home, forbidding travel, limiting visitors, and temperature screening. Others are more unique to the fab operation. For example, workers are split into two teams that never come into contact with each other; they aren’t in the building on the same day, and they even use separate gowning rooms to enter the cleanroom floor. Those gowning rooms are marked off in roughly 2-meter squares, and no two people are allowed to occupy the same square.
Once employees are suited up and in the clean room, they’re taking advantage of it. “It’s one of the cleanest places on earth,” says Sampson. “We’ve moved all of our operations meetings onto the factory floor itself,” instead of having physically separated team members in a conference room.
GlobalFoundries is sharing some of what makes that safety possible, too. It’s assisted healthcare facilities in New York and Vermont, where its U.S. fabs are located, with available personal protective equipment, such as face shields and masks, in addition to making cash donations to local food banks and other causes near its fabs around the world. (SkyWater is currently evaluating what the most significant needs are in its community and whether it is able to play a meaningful role in addressing them.)
But there are plenty of similarities with GlobalFoundries in SkyWater’s current operations, including telecommuting engineers, staggered in-person work shifts, and restricted entry for visitors. There are, of course, few visitors these days. Customers and technology development partners are meeting remotely with SkyWater’s engineers. And many chip making tools can be monitored by service companies remotely.
(Applied Materials, a major chip equipment maker, says that many customers’ tools are monitored and diagnosed remotely already. The company installs a server in the fab that allows field engineers access to the tools without having to set foot on premises.)
With the whole world in economic upheaval, you might expect that the crisis would lead to some surprises in foundry supply chains. Both GlobalFoundries and SkyWater say they are well prepared. For SkyWater, a relatively small US-based foundry with just the one fab, the big reasons for that preparedness was the trade war between the United States and China beginning in 2018.
“If you look at the broader supply chain, we’ve been preparing for this since tariffs began,” says Sonderman. Those necessitated a deep dive into the business’s potential vulnerabilities that’s helped guide the response to the current crisis, he says.
At press time no employees of either company had tested positive for the virus. But that situation is likely to change as the virus spreads, and the companies say they will adapt. Like everybody else, “we’re finding our new normal,” says Sampson.
The result is an efficient solar heating metamaterial that can heat up rapidly to 83 degrees C (181 degrees F) in an open environment with minimal heat loss. Proposed applications for the film include thermal energy harvesting and storage, thermoelectricity generation, and seawater desalination.
Since topological insulators were first created in 2007, these novel materials, which are insulating on the inside and conductive on the outside, have intrigued researchers for their potential in electronics. However, a related but more obscure class of materials—topological photonics—may reach practical applications first.
Topology is the branch of mathematics that investigates what aspects of shapes withstand deformation. For example, an object shaped like a ring may deform into the shape of a mug, with the ring’s hole forming the hole in the cup’s handle, but cannot deform into a shape without a hole.
Using insights from topology, researchers developed topological insulators. Electrons traveling along the edges or surfaces of these materials strongly resist any disturbances that might hinder their flow, much as the hole in a deforming ring would resist any change.
Recently, scientists have designed photonic topological insulators in which light is similarly “topologically protected.” These materials possess regular variations in their structures that lead specific wavelengths of light to flow along their exterior without scattering or losses, even around corners and imperfections.
Here are three promising potential uses for topological photonics.
TOPOLOGICAL LASERS Among the first practical applications of these novel materials may be lasers that incorporate topological protection. For example, Mercedeh Khajavikhan of the University of Southern California and her colleagues developed topological lasers that were more efficient and proved more robust against defects than conventional devices.
The researchers started with a wafer made of gallium arsenide and aluminum gallium arsenide layers sandwiched together. When electrically charged, the wafer emitted bright light.
The scientists drilled a lattice of holes into the wafer. Each hole resembled an equilateral triangle with its corners snipped off. The lattice was surrounded by holes of the same shape oriented the opposite way.
The topologically protected light from the wafer flowed along the interface between the different sets of holes, and emerged from nearby channels as laser beams. The device proved robust against defects, says electrical and optical engineer Qi Jie Wang at Nanyang Technological University in Singapore.
The laser works in terahertz frequencies, which are useful for imaging and security screening. Khajavikhan and her colleagues are now working to develop ones that work at near-infrared wavelengths, possibly for telecommunications, imaging, and lidar.
PHOTONIC CHIPS By using photons instead of electrons, photonic chips promise to process data more quickly than conventional electronics can, potentially supporting high-capacity data routing for 5G or even 6G networks. Photonic topological insulators could prove especially valuable for photonic chips, guiding light around defects.
However, topological protection works only on the outsides of materials, meaning the interiors of photonic topological insulators are effectively wasted space, greatly limiting how compact such devices can get.
To address this problem, optical engineer Liang Feng at the University of Pennsylvania and his colleagues developed a photonic topological insulator with edges they could reconfigure so the entire device could shuttle data. They built a photonic chip 250 micrometers wide and etched it with oval rings. By pumping the chip with an external laser, they could alter the optical properties of individual rings, such that “we could get the light to go anywhere we wanted in the chip,” Feng says—from any input port to any output port, or even multiple outputs at once.
All in all, the chip hosted hundreds of times as many ports as seen in current state-of-the-art photonic routers and switches. Instead of requiring an off-chip laser to reconfigure the chip, the researchers are now developing an integrated way to perform that task.
QUANTUM CIRCUITRYQuantum computers based on qubits are theoretically extraordinarily powerful. But qubits based on superconducting circuits and trapped ions are susceptible to electromagnetic interference, making it difficult to scale up to useful machines. Qubits based on photons could avoid such problems.
Quantum computers work only if their qubits are “entangled,” or linked together to work as one. Entanglement is very fragile—researchers hope topological protection could defend photonic qubits from scattering and other disruptions that can occur when photons run across inevitable fabrication errors.
Photonic scientist Andrea Blanco-Redondo, now head of silicon photonics at Nokia Bell Labs, and her colleagues made lattices of silicon nanowires, each 450 nanometers wide, and lined them up in parallel. Occasionally a nanowire in the lattice was separated from the others by two thick gaps. This generated two different topologies within the lattice and entangled photons traveling down the border between these topologies were topologically protected, even when the researchers added imperfections to the lattices. The hope is that such topological protection could help quantum computers based on light scale up to solve problems far beyond the capabilities of mainstream computers.
This article appears in the April 2020 print issue as “3 Practical Uses for Topological Photonics.”
There’s been a lot of intense and well-funded work developing chips that are specially designed to perform AI algorithms faster and more efficiently. The trouble is that it takes years to design a chip, and the universe of machine learning algorithms moves a lot faster than that. Ideally you want a chip that’s optimized to do today’s AI, not the AI of two to five years ago. Google’s solution: have an AI design the AI chip.
“We believe that it is AI itself that will provide the means to shorten the chip design cycle, creating a symbiotic relationship between hardware and AI, with each fueling advances in the other,” they write in a paper describing the work that posted today to Arxiv.
“We have already seen that there are algorithms or neural network architectures that… don’t perform as well on existing generations of accelerators, because the accelerators were designed like two years ago, and back then these neural nets didn’t exist,” says Azalia Mirhoseini, a senior research scientist at Google. “If we reduce the design cycle, we can bridge the gap.”
Mirhoseini and senior software engineer Anna Goldie have come up with a neural network that learn to do a particularly time-consuming part of design called placement. After studying chip designs long enough, it can produce a design for a Google Tensor Processing Unit in less than 24 hours that beats several weeks-worth of design effort by human experts in terms of power, performance, and area.
Placement is so complex and time-consuming because it involves placing blocks of logic and memory or clusters of those blocks called macros in such a way that power and performance are maximized and the area of the chip is minimized. Heightening the challenge is the requirement that all this happen while at the same time obeying rules about the density of interconnects. Goldie and Mirhoseini targeted chip placement, because even with today’s advanced tools, it takes a human expert weeks of iteration to produce an acceptable design.
Goldie and Mirhoseini modeled chip placement as a reinforcement learning problem. Reinforcement learning systems, unlike typical deep learning, do not train on a large set of labeled data. Instead, they learn by doing, adjusting the parameters in their networks according to a reward signal when they succeed. In this case, the reward was a proxy measure of a combination of power reduction, performance improvement, and area reduction. As a result, the placement-bot becomes better at its task the more designs it does.
The team hopes AI systems like theirs will lead to the design of “more chips in the same time period, and also chips that run faster, use less power, cost less to build, and use less area,” says Goldie.
Are you interested in modelling piezoelectric sensors and actuators? If so, then join us for this webinar.
In this webinar, James Ransley from Veryst Engineering will work through a case study in which the properties of a piezoelectric bender actuator are optimized. The material orientation and dimensions are optimized to maximize the efficiency of the bender for the application. The blocking curve is computed and the dimensions are modified to achieve a given specification with minimal actuator volume.
The study will also include a live demo of piezoelectric device design using the COMSOL Multiphysics® simulation software. A Q&A session will conclude the webinar.
Optimal crystal orientation and displacement profile (color is proportional to relative displacement) for a piezoelectric bender made from lithium niobate (left) and PZT 5H (right).
Israeli startup Hailo says it has raised US $60 million in the second round of funding it will use to mass produce its Hailo-8 chip. The Hailo-8 is designed to do deep learning in cars, robots, and other “edge” machines. Such edge chips are meant to reduce the cost, size, and power consumption needs of using AI to process high-resolution information from sensors such as HD cameras.
In novel materials known as photonic topological insulators, wavelengths of light can flow around sharp corners with virtually no losses. Now scientists have witnessed key details of what the light does inside these structures, which could help them to better engineer these materials for real-world applications.
Topology is the branch of mathematics that explores what features of shapes withstand deformation. For instance, an object shaped like a doughnut can get pushed and pulled into the shape of a mug, with the doughnut’s hole forming the hole in the cup’s handle, but it could not get deformed into a shape that lacked a hole.
Using insights from topology, researchers developed the first electronic topological insulators in 2007. Electrons traveling along the edges or surfaces of these materials strongly resist any disturbances that might hinder their flow, much as a doughnut might resist any change that would remove its hole.
French startup Cartesiam was founded because of the predicted inundation of IoT sensors and products. Even a few years ago, the idea was that these tens of billions of smart sensors would deliver their data to the cloud. AI and other software there would understand what it meant and trigger the appropriate action.
As it did to many others in the embedded systems space, this scheme looked a little ludicrous. “We were thinking: it doesn’t make sense,” says general manager and cofounder Marc Dupaquier. Transporting all that data was expensive in terms of energy and money, it wasn’t secure, it added latency between an event and the needed reaction, and it was a privacy-endangering use of data. So Cartesiam set about building a system that allows ordinary Arm microcontrollers to run a kind of AI called unsupervised learning.
Societies in Africa, the Amazon basin, and New Guinea used to send messages over long distances by banging on drums. Now a group of scientists in the United Kingdom is adapting that idea, using sound pulses to speed up the transmission of data.
Data centers and satellite relays have vast amounts of information to send from one place to another, so speeding up transmission would help enormously. Quantum cascade lasers (QCLs) can emit light at terahertz frequencies, but data has to be encoded onto the laser beam, and the basic laws of physics place a limit on how fast electronic systems can modulate the beam.
So engineers from the University of Leeds and the University of Nottingham in England decided to skip the electronics and use an acoustic wave to modulate the light instead. They describe their proof-of-concept in a recent paper in Nature Communications.
A QCL consists of a series of quantum wells, small areas that confine electrons at specific energy levels. As an electron drops from one well to the next in a sort of waterfall effect, it emits a photon, so a single electron can produce many photons.
To modulate the emission of those photons, and thus encode data onto the laser beam, the research team attached a thin aluminum film to one contact of the laser. They then hit the film with pulses from a different type of laser. Each brief pulse caused the aluminum skin to produce an acoustic wave that ran through the QCL, slightly deforming the structure.
“It’s as if the whole system’s being shaken really,” says John Cunningham, a professor of electronic and electrical engineering at Leeds who led the research. “It changes the probability of electron transfer between the quantum wells.”
The team used an off-the-shelf QCL to create its prototype system, and only achieved modulation of about 6 percent. Cunningham says it should be possible to reach 100 percent modulation by redesigning the laser so that the quantum wells are specifically engineered to respond to acoustic waves. He’d also like to incorporate a semiconductor phonon laser—a saser, the sonic equivalent of a laser—invented by Tony Kent, a professor of physics at Nottingham and a co-author of the paper. That would make the system more compact and efficient.
Electronic circuits, limited by inductance, capacitance, and resistance, can modulate a laser at a few tens of gigahertz at most. Cunningham says an acoustic system should increase that to hundreds of gigahertz for a tenfold increase in transmission speed, and might one day get even faster.
For decades, the trend was for more and more of a computer’s systems to be integrated onto a single chip. Today’s system-on-chips, which power smartphones and servers alike, are the result. But complexity and cost are starting to erode the idea that everything should be on a single slice of silicon.
Already, some of the most of advanced processors, such as AMD’s Zen 2 processor family, are actually a collection of chiplets bound together by high-bandwidth connections within a single package. This week at the IEEE Solid-State Circuits Conference (ISSCC) in San Francisco, French research organization CEA-Leti showed how far this scheme can go, creating a 96-core processor out of six chiplets.
Using an unrelated technology the company had in development, Eta Compute pivoted toward more traditional neural networks such as deep learning and is reaping the rewards. The West Lake Village, Calif.-based company revealed on Wednesday that its first production chips using that technology are now shipping.
Quantum measurements, at the core of next-generation technologies including quantum computing, quantum cryptography, and ultra-sensitive electronics, may face a new hurdle as system sensitivities brush up against Heisenberg’s Uncertainty Principle.
The practical Heisenberg limits in measuring some quantities up to the ultimate quantum sensitivity may be larger than expected—by a factor of pi. This new finding would, according to physicist Wojciech Górecki of the University of Warsaw in Poland, represent “an impediment compared to previous expectations.”
Górecki said he and his collaborators arrived at this theoretical limit by applying a branch of math known as Bayesian statistics to familiar quantum measurement problems.
The standard problem posed in many Intro to Quantum classes involves the push-and-pull conflict between measuring a particle’s position with high precision versus knowing that same particle’s momentum with high precision as well.
So, down at the quantum scale, there are always tradeoffs. Measuring a particle’s position with very high precision calls for sacrificing how precisely you can determine the speed and direction of its travel.
Yet, said Górecki, plenty of quantum scale measurements involve neither position nor momentum. For instance, some photonics instruments measure quantities like the phase of a wavefront versus the number of photons counted in a given energy range.
Górecki notes that canonical Heisenberg isn’t as much help here as is a related concept called the “Heisenberg limit.” The Heisenberg Limit, he says, delineates the smallest possible uncertainty in a measurement, given a set number of times a system is probed. “It is a natural consequence of Heisenberg’s uncertainty principle, interpreted in a slightly broader context,” says Górecki.
It was long believed that, with a hypothetical technology trying to discover phase as precisely as possible using only n photons, the Heisenberg Limit to the uncertainty in phase was 1/n. But no technology had been devised to prove that 1/n was the ultimate universal “Heisenberg Limit.”
There’s a good reason why. Górecki and colleagues report in a new paper in the journal Physical Review Letters that the Heisenberg Limit in this case scales as π/n instead of 1/n. In other words, the smallest measurable uncertainty is more than three times as much as previously believed. And so now we know that our observations of the universe are a little bit fuzzier than we imagined.
(To be clear, “n” here is not necessarily just the number of photons used in a measurement. It could also represent a number of other limits on the amount of resources expended in making a precision observation. The variable “n” here could also be, Górecki notes, the number of quantum gates in a measurement or the total time spent interrogating the system.)
Górecki says the new finding may not remain purely theoretical for too much longer. A 2007 experiment in precision phase measurement came within 56 percent of the new Heisenberg Limit.
“Our paper has attracted the interest of eminent researchers in the field of statistics, which find this idea worth spreading,” says Górecki. “Perhaps it would be possible to construct a simpler proof that could be included in standard textbooks.”
Processing images to allow self-driving cars to see where they’re going could get easier thanks to a specially sculpted lens that does the work of a computer.
Dutch and American researchers say they can use a metasurface to passively detect the edges of objects in video. Computers can perform such edge detection for autonomous vehicles or virtual reality applications, but that uses power and is not instantaneous. “If you want to do that digitally, it takes time for the computer to compute,” says Albert Polman, who heads the Light Management in New Photovoltaic Materials group at AMOLF, a scientific research institute in Amsterdam, the Netherlands.
In a paper in Nano Letters, Polman and colleagues describe how their material performs the mathematical operations necessary for edge detection. They built a metasurface, which is studded with tiny pillars, smaller than the wavelength of light, which can manipulate light in unusual ways based on their size and arrangement. In this case, they started with a thin sheet of sapphire, less than half a millimeter thick, and added pillars of silicon that were 206 nm thick, 142 nm tall, and spaced 300 nm apart.
When placed on the surface of a standard CCD chip, the metasurface acts like a lens, passing light that strikes it at steep angles but filtering out light hitting it at very slight angles. The features of an image are built from combinations of different light waves, and the waves that get filtered out carry the fine details of the image, leaving only the sharper components, such as the edges of a person’s face compared to the whiteboard behind her.
Depending on the computer and the size of the image, it might take several milliseconds to process this information digitally. With the analog approach, only limiting factor is the thickness of the metasurface. “It’s just the time light takes to travel 150 nm, which is basically nothing,” Polman says.
It’s also a passive technique. “It’s just a piece of glass, so you don’t need to give it power,” he says. Of course, the digital camera and a computer would still have a role, but Polman says this hybrid approach should be more efficient.
The researchers would like to try other materials, such as titanium oxide or silicon nitride, to see if they can get even better results. And while this metasurface captures edges in one dimension, they’d like to try two-dimensional designs, so they can capture edges at different orientations.
MicroLEDs appear to be, forgive the pun, the bright future of displays. Made of micrometer-scale gallium-nitride LEDs, the technology offers an unmatchable ratio of brightness to power consumption.
The problem is that the most easily manufacturable ones are so small they’re suitable only for augmented reality and similar applications. Making bigger ones, like for a watch display or a smartphone screen, requires the near-perfect transfer of tens of thousands of individual microLEDs per second onto a prefabricated silicon backplane. It’s a very difficult proposition, but Apple and some startups are trying to tackle it.
If New Mexico-based startup iBeam is correct, even larger microLED displays could be produced quickly and cheaply on flexible substrates. “iBeam is a new paradigm in manufacturing for microLEDs,” says Julian Osinski, the startup’s vice president of product technology. “We have a way of growing microLEDs directly on a roll of metal foil, and that’s something nobody else can do.”
iBeam’s technology is adapted from the superconductor manufacturing industry where something similar has produced product by the kilometer. Founder and CEO Vladimir Matias is a superconductor manufacturing veteran and saw its potential in producing gallium-nitride devices.
LEDs and other gallium-nitride devices are usually grown atop a silicon or sapphire wafer by a process called epitaxy. For that to work, you need a single crystal, preferably with a similar crystal structure, for the gallium nitride to grow on. The iBeam process can produce that crystal-like substrate on an otherwise amorphous or polycrystalline surface such as metal or glass.
When you deposit material on an amorphous substrate you normally get a film of randomly oriented grains of crystal, explains Matias. But briefly blasting that film with ions from just the right angle gets all the grains to line up. iBeam chooses the film’s material so that the aligned grains match well with gallium nitride’s crystal structure. From there, they grow layers of gallium nitride using standard techniques and fashion them into microLEDs. Quantum dots will then be added to convert the color of some of the microLEDs from their natural blue to red and green.
Just as is done with superconductors, the procedure could be rapidly done in a roll-to-roll fashion, Osinski says. Today’s industry processes produce gallium nitride for about US $2 to $3 per square centimeter. “We’d like to take it down to 10 cents [per square centimeter] or less so it becomes competitive with OLEDs,” he says.
The company has used its existing process to produce microLEDs, and last month it announced the production of high-electron mobility transistors (HEMTs), as well. If the HEMTs could be constructed along with the microLEDs, they could form the circuitry that controls the microLED pixels.
(Kei May Lau’s team at Hong Kong University of Science and Technology developed a structure that integrates the HEMT and microLED so tightly that they effectively become one device.)
The startup’s near-term goal is to produce a small prototype display, which Osinki thinks may take until the end of next year. They hope to have large-scale manufacturing nailed down by 2022. That’s later than some microLED firms are planning to commercialize their products, but iBeam is counting on being able to produce much larger displays and at much lower cost. The company plans to sell its manufacturing process and materials to established display makers rather than become a manufacturer itself.
Graphene can literally be made in a flash by using electricity to zap nearly anything that contains carbon, including discarded food and plastic, a new study finds.
Graphene is made of flexible, transparent sheets each just one carbon atom thick. It’s 200 times stronger than steel, lighter than paper, and more electrically and thermally conductive than copper. Currently the most common way to make graphene in bulk is via exfoliation. It works a bit like how you might exfoliate your skin, and involves sloughing layers of graphene off a block of graphite.
However, chemical exfoliation uses lots of acid and is very expensive, while exfoliation using sound energy or fast-flowing fluid pries off platelets of graphene that are often more than 20 layers thick. Scientists can also produce graphene by depositing it from a vapor onto a surface, but this only makes tiny amounts.
The kind of memory most people are familiar with returns data when given an address for that data. Content addressable memory (CAM) does the reverse: When given a set of data, it returns the address—typically in a single clock cycle—of where to find it. That ability, so useful in network routers and other systems that require a lot of lookups, is now getting a chance in new kinds of data-intensive tasks such as pattern matching and accelerating neural networks, as well as for doing logic operations in the memory itself.
Practically any kind of crap can boost graphene’s properties as a catalyst—even chicken droppings, say the authors of a new tongue-in-cheek study.
Graphene is often hailed as a wonder material—flexible, transparent, light, strong, and electrically and thermally conductive. Such qualities have led researchers worldwide to consider weaving these one-atom-thick sheets of carbon into advanced devices. Scientists have also explored graphene’s properties as a catalyst for the kinds of oxygen reduction reactions often used in fuel cells and the hydrogen evolution reactions used to split apart water molecules to generate hydrogen fuel.
To further enhance graphene’s catalytic properties, researchers have tried doping it with a variety of elements. Seemingly all such studies have claimed graphene’s catalytic abilities improved, regardless of whether the doping materials had contrasting properties with each other. This is “contrary to what any material scientist might expect,” says Martin Pumera, a materials scientist at the University of Chemistry and Technology in Prague.
Researchers in California have extended the spectral range of perovskite light-emitting diodes into the blues. How did they do it? By cracking the mystery of why the optical and electronic properties of the materials change when current flows through them.
Painstaking measurements revealed that current-induced heating deformed cells in the semiconductor crystals. That observation enabled the team to make the first single-crystal perovskite diodes, says group leader Peidong Yang, a chemistry professor at the University of California at Berkeley.
If there’s one thing about Moore’s Law that’s obvious to anyone, it’s that transistors have been made smaller and smaller as the years went on. Scientists and engineers have taken that trend to an almost absurd limit during the past decade, creating devices that are made of one-atom-thick layers of material.
The most famous of these materials is, of course, graphene, a hexagonal honeycomb-shaped sheet of carbon with outstanding conductivity for both heat and electricity, odd optical abilities, and incredible mechanical strength. But as a substance with which to make transistors, graphene hasn’t really delivered. With no natural bandgap—the property that makes a semiconductor a semiconductor—it’s just not built for the job.
Instead, scientists and engineers have been exploring the universe of transition metal dichalcogenides, which all have the chemical formula MX2. These are made up of one of more than a dozen transition metals (M) along with one of the three chalcogenides (X): sulfur, selenium, or tellurium. Tungsten disulfide, molybdenum diselenide, and a few others can be made in single-atom layers that (unlike graphene) are natural semiconductors. These materials offer the enticing prospect that we will be able to scale down transistors all the way to atom-thin components long after today’s silicon technology has run its course.
While this idea is really exciting, I and my colleagues at Imec believe 2D materials could actually show up much sooner, even while silicon still remains king. We’ve been developing a technology that could put 2D semiconductors to work in silicon chips, enhancing their abilities and simplifying their designs.
Devices made with 2D materials are worth all the scientific and engineering work we and other researchers around the world have put into them because they could eliminate one of the biggest problems with today’s transistors. The issue, the result of what are called short-channel effects, is a consequence of the continual shrinking of the transistor over the decades.
A metal-oxide semiconductor field-effect transistor (MOSFET), the type of device in all digital things, is made up of five basic parts: The source and drain electrodes; the channel region that connects them; the gate dielectric, which covers the channel on one or more sides; and the gate electrode, which contacts the dielectric. Applying a voltage at the gate relative to the source creates a layer of mobile charge carriers in the channel region that forms a conductive bridge between the source and drain, allowing current to flow.
But as the channel was made smaller and smaller, current would increasingly leak across it even when there was no voltage on the gate, wasting power. The change from the planar designs of the 20th century to the FinFET transistor structure used in today’s most advanced processors was an attempt to counter this important short-channel effect by making the channel region thinner and having the gate surround it on more sides. The resulting fin-shaped structure provides better electrostatic control. (The coming move to the nanosheet transistor is a furthering of this same idea. See “The Last Silicon Transistor,” IEEE Spectrum, August 2019.)
Certain 2D semiconductors could circumvent short-channel effects, we think, by replacing the silicon in the device channel. A 2D semiconductor provides a very thin channel region—as thin as a single atom if only one layer of semiconductor is used. With such a restricted pathway for current to flow, there is little opportunity for charge carriers to sneak across when the device is meant to be off. That means the transistor could continue to be shrunk down further with less worry about the consequences of short-channel effects.
These 2D materials are not only useful as semiconductors, though. Some, such as hexagonal boron nitride, can act as gate dielectrics, having a dielectric constant similar to that of silicon dioxide, which was routinely used for that job until about a decade ago. Add graphene in place of the transistor’s metal parts and you’ve got a combination of 2D materials that forms a complete transistor. Indeed, separate groups of researchers built such devices as far back as 2014. While these prototypes were much larger, you could imagine scaling them down to the size of just a few nanometers.
As amazing as an all-2D transistor that’s a fraction of the size of today’s devices might be, that won’t be the first implementation of 2D materials in electronic circuits. Instead, 2D materials will probably arrive in low-power circuits that have more relaxed performance requirements and area constraints.
The set of circuits we’re targeting at Imec are built in the so-called back-end-of-line. Chipmaking is divided into two parts: the front-end-of-line part consists of processes—many of them requiring high temperatures—that alter the silicon itself, such as implanting dopants to define the parts of a transistor. The back-end-of-line part builds the many layers of interconnects that link the transistors to form circuits and deliver power.
With traditional transistor scaling becoming more and more difficult, engineers have been looking for ways to add functionality to the interconnect layers. You can’t do this simply by using ordinary silicon processes because the heat involved would damage the devices and interconnects beneath them. So, many of these schemes rely on materials that can be made into devices at relatively low temperatures.
A specific advantage of using 2D semiconductors instead of some other candidates is the potential ability to build both p-type (carrying positive charges) and n-type (carrying electrons) devices, a necessity in CMOS logic. CMOS circuits are the backbone of today’s logic because, ideally, they consume power only when switching from one state to the other. In our preferred 2D semiconductor, we’ve demonstrated n-type transistors but not yet p-type. However, the physics underlying these materials strongly suggests we can get there through engineering the dielectrics and metals that contact the semiconductor.
Being able to produce both p– and n-type devices would allow the development of compact back-end logic circuits such as repeaters. Repeaters essentially relay data that must travel relatively far across a chip. Ordinarily, the transistors involved reside on the silicon, but that means signals must climb up the stack of interconnects until they reach a layer where they can travel part of the distance to their destination, then go back down to the silicon to be repeated and up again to the long-distance interconnect layer. It’s a bit like having to exit the highway and drive into the center of a crowded city to buy petrol before getting back on the highway.
A repeater up near the long-distance interconnect layer is more akin to a motorway petrol station. It saves the time it would take the signal to make the two-way vertical trip and also prevents the loss of power due to the resistance of the vertical interconnects. What’s more, moving the repeater to the interconnect layer saves space on the silicon for more logic.
Repeaters aren’t the only potential use. A 2D material could also be used to build other circuits, such as on-chip power-management systems, signal buffers, and memory selectors. One thing these circuits all have in common is that they don’t require the device to drive a lot of current, so one layer of 2D material would probably be sufficient.
Neither future supersmall 2D devices nor the less demanding back-end-of-line circuits will be possible without a fabrication process compatible with industry-standard 300-millimeter silicon wafers. So our team at Imec is working on just that, hoping to develop a process that will serve for all applications.
The first step is identifying the most promising 2D material and device architecture. We have therefore benchmarked a variety of 2D semiconductors and 2D FET architectures against an advanced silicon FinFET device.
Because researchers have the most experience with molybdenum disulfide (MoS2), experimental devices made using it have advanced furthest. Indeed, at the IEEE International Electron Device Meeting last December, Imec unveiled an MoS2 transistor with a channel just 30 nanometers across and source and drain contacts only 13 nm long. But after examining the possibilities, we’ve decided that MoS2 is not the answer. Instead, we concluded that among all the materials compatible with 300-mm silicon-wafer technology, tungsten disulfide (WS2) in the form of a stacked nanosheet device has the highest performance potential, meaning it can drive the most current. For less demanding, back-end-of-line applications, we also concluded that a FET architecture with a gate both below and above the semiconductor channel region works better than one with only a single gate.
We already knew one important thing about WS2 before we reached that conclusion: We can make a high-quality version of it on a 300-mm silicon wafer. We demonstrated that for the first time in 2018 by growing the material on a wafer using metal-organic chemical vapor deposition (MOCVD), a common process that grows crystals on a surface by means of a chemical reaction. The approach we took results in thickness control down to a single-molecule layer, or monolayer, over the full 300-mm wafer. The benefits of the MOCVD growth come, however, at the price of a high temperature—and recall that high temperatures are forbidden in back-end processes because they could damage the silicon devices below.
To get around this problem, we grow the WS2 on a separate wafer and then transfer it to the already partially fabricated silicon wafer. The Imec team developed a unique transfer process that allows a single layer of WS2—as thin as 0.7 nm—to be moved to a silicon target wafer with negligible degradation in the 2D material’s electrical properties.
The process starts by growing the WS2 on an oxide-covered silicon wafer. That’s then placed in contact with a specially prepared wafer. This wafer has a layer of material that melts away when illuminated by a laser. It also has a coating of adhesive. The adhesive side is pressed to the WS2-covered wafer, and the 2D material peels away from the growth wafer and sticks to the adhesive. Then the adhesive wafer with its 2D cargo is flipped over onto the target silicon wafer, which in a real chipmaking effort would already have transistors and several layers of interconnect on it. Next, a laser is shone through the wafer to break the bulk of it away, leaving only the adhesive and the WS2 atop the target wafer. The adhesive is removed with chemicals and plasma. What’s left is just the processed silicon with the WS2 attached to it, held in place by Van der Waals forces.
The process is complicated, but it works. There is, of course, room for improvement, most importantly in mitigating defects caused by unwanted particles on the wafer surface and in eliminating some defects that occur at the edges.
Once the 2D semiconductor has been deposited, building devices can begin. On that front there have been triumphs, but some major challenges remain.
Perhaps the most crucial issue to tackle is the creation of defects in the WS2. Imperfections profoundly degrade the performance of a 2D device. In ordinary silicon devices, charge can get caught in imperfections at the interface between the gate dielectric and the channel region. These can scatter electrons or holes near the interface as they try to move through the device, slowing things down. With 2D semiconductors the scattering problem is more pronounced because the interface is the channel.
Sulfur vacancies are the most common defects that affect device channel regions. Imec is investigating how different plasma treatments might make those vacancies less chemically reactive and therefore less prone to alter the transistor’s behavior. We also need to prevent more defects from forming after we’ve grown the monolayer. WS2 and other 2D materials are known to age quickly and degrade further if already defective. Oxygen attacking a sulfur vacancy can cause more vacancies nearby, making the defect area grow larger and larger. But we’ve found that storing the samples in an inert environment makes a difference in preventing that spread.
Defects in the semiconductor aren’t the only problems we’ve encountered trying to make 2D devices. Depositing insulating materials on top of the 2D surface to form the gate dielectric is a true challenge. WS2 and similar materials lack dangling bonds that would otherwise help fasten the dielectric to the surface.
Our team is currently exploring two routes that might help: One is atomic layer deposition (ALD) at a reduced growth temperature. In ALD, a gaseous molecule adsorbs to the semiconductor’s exposed surface to form a single layer. Then a second gas is added, reacting with the adsorbed first one to leave an atomically precise layer of material, such as the dielectric hafnium dioxide. Doing this at a reduced temperature increases the ability of the gas molecules to stick to the surface of the WS2 even when no chemical bonds are available.
The other option is to enhance ALD by using a very thin oxidized layer, such as silicon oxide, to help nucleate the growth of the ALD layer. A very thin layer of silicon is deposited by a physical deposition method such as sputtering or evaporation; it’s then oxidized before a regular ALD deposition of gate oxide is done. We’ve achieved particularly good results with evaporation.
A further challenge in making superior 2D devices is in choosing the right metals to use as source and drain contacts. Metals can alter the characteristics of the device, depending on their work function. That parameter, the minimum energy needed to extract an electron from the metal, can mean the difference between a contact that can easily inject electrons and one that can inject holes. So the Imec team has screened a variety of metals to put in contact with the WS2 nanosheet. We found that the highest on-current in an n-type device was obtained using a magnesium contact, but other metals such as nickel or tungsten work well. We’ll be searching for a different metal for future p-type devices.
Despite these challenges, we’ve been able to estimate the upper limits of device performance, and we’ve mapped out what roads to follow to get there.
As a benchmark, the Imec team used dual-gated devices like those we described earlier. We built them with small, naturally exfoliated flakes of WS2, which have fewer defects than wafer-scale semiconductors. For these lab-scale devices, we were able to measure electron mobility values up to a few hundred square centimeters per volt-second, which nearly matches crystalline silicon and is close to the theoretically predicted maximum for the 2D material. Because this excellent mobility can be found in natural material, we are confident that it should also be possible to get there with materials synthesized on 300-mm wafers, which currently reach just a few square centimeters per volt-second.
For some of the main challenges ahead in 2D semiconductor development, our team has a clear view of the solutions. We know, for example, how to grow and transfer the material onto a 300-mm target wafer; we’ve got an idea of how to integrate the crucial gate dielectric; and we’re on a path to boost the mobility of charge carriers in devices toward a level that could compare with silicon.
But, as we’ve laid out, there are still significant problems remaining. These will require an intensive engineering effort and an even better fundamental understanding of this new class of intriguing 2D materials. Solving these challenges will enable high-performance devices that are scaled down to atomic layers, but they might first bring new capabilities that need less demanding specifications even as we continue to scale down silicon.
This article appears in the February 2020 print issue as “Atom-Thick Transistors.”
About the Author
Iuliana Radu is program director at Imec, in Leuven, Belgium, where she leads the research center’s Beyond CMOs program and quantum computing activities.
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