Tag Archives: Semiconductors

Chicken Droppings Can Make Graphene More Catalytic

Post Syndicated from Charles Q. Choi original https://spectrum.ieee.org/nanoclast/semiconductors/materials/graphene-doping-catalyst-materials-research-news

Practically any kind of crap can boost graphene’s properties as a catalyst—even chicken droppings, say the authors of a new tongue-in-cheek study.

Graphene is often hailed as a wonder material—flexible, transparent, light, strong, and electrically and thermally conductive. Such qualities have led researchers worldwide to consider weaving these one-atom-thick sheets of carbon into advanced devices. Scientists have also explored graphene’s properties as a catalyst for the kinds of oxygen reduction reactions often used in fuel cells and the hydrogen evolution reactions used to split apart water molecules to generate hydrogen fuel.

To further enhance graphene’s catalytic properties, researchers have tried doping it with a variety of elements. Seemingly all such studies have claimed graphene’s catalytic abilities improved, regardless of whether the doping materials had contrasting properties with each other. This is “contrary to what any material scientist might expect,” says Martin Pumera, a materials scientist at the University of Chemistry and Technology in Prague.

First Blue LED Emission From a Perovskite

Post Syndicated from Jeff Hecht original https://spectrum.ieee.org/tech-talk/semiconductors/materials/first-blue-led-emission-perovskite-news

Researchers in California have extended the spectral range of perovskite light-emitting diodes into the blues. How did they do it? By cracking the mystery of why the optical and electronic properties of the materials change when current flows through them.

Painstaking measurements revealed that current-induced heating deformed cells in the semiconductor crystals. That observation enabled the team to make the first single-crystal perovskite diodes, says group leader Peidong Yang, a chemistry professor at the University of California at Berkeley. 

Coming Soon to a Processor Near You: Atom-Thick Transistors


Post Syndicated from Iuliana Radu original https://spectrum.ieee.org/semiconductors/materials/coming-soon-to-a-processor-near-you-atomthick-transistors

If there’s one thing about Moore’s Law that’s obvious to anyone, it’s that transistors have been made smaller and smaller as the years went on. Scientists and engineers have taken that trend to an almost absurd limit during the past decade, creating devices that are made of one-atom-thick layers of material.

The most famous of these materials is, of course, graphene, a hexagonal honeycomb-shaped sheet of carbon with outstanding conductivity for both heat and electricity, odd optical abilities, and incredible mechanical strength. But as a substance with which to make transistors, graphene hasn’t really delivered. With no natural bandgap—the property that makes a semiconductor a semiconductor—it’s just not built for the job.

Instead, scientists and engineers have been exploring the universe of transition metal dichalcogenides, which all have the chemical formula MX2. These are made up of one of more than a dozen transition metals (M) along with one of the three chalcogenides (X): sulfur, selenium, or tellurium. Tungsten disulfide, molybdenum diselenide, and a few others can be made in single-atom layers that (unlike graphene) are natural semiconductors. These materials offer the enticing prospect that we will be able to scale down transistors all the way to atom-thin components long after today’s silicon technology has run its course.

While this idea is really exciting, I and my colleagues at Imec believe 2D materials could actually show up much sooner, even while silicon still remains king. We’ve been developing a technology that could put 2D semiconductors to work in silicon chips, enhancing their abilities and simplifying their designs.

Devices made with 2D materials are worth all the scientific and engineering work we and other researchers around the world have put into them because they could eliminate one of the biggest problems with today’s transistors. The issue, the result of what are called short-channel effects, is a consequence of the continual shrinking of the transistor over the decades.

A metal-oxide semiconductor field-effect transistor (MOSFET), the type of device in all digital things, is made up of five basic parts: The source and drain electrodes; the channel region that connects them; the gate dielectric, which covers the channel on one or more sides; and the gate electrode, which contacts the dielectric. Applying a voltage at the gate relative to the source creates a layer of mobile charge carriers in the channel region that forms a conductive bridge between the source and drain, allowing current to flow.

But as the channel was made smaller and smaller, current would increasingly leak across it even when there was no voltage on the gate, wasting power. The change from the planar designs of the 20th century to the FinFET transistor structure used in today’s most advanced processors was an attempt to counter this important short-channel effect by making the channel region thinner and having the gate surround it on more sides. The resulting fin-shaped structure provides better electrostatic control. (The coming move to the nanosheet transistor is a furthering of this same idea. See “The Last Silicon Transistor,” IEEE Spectrum, August 2019.)

Certain 2D semiconductors could circumvent short-channel effects, we think, by replacing the silicon in the device channel. A 2D semiconductor provides a very thin channel region—as thin as a single atom if only one layer of semiconductor is used. With such a restricted pathway for current to flow, there is little opportunity for charge carriers to sneak across when the device is meant to be off. That means the transistor could continue to be shrunk down further with less worry about the consequences of short-channel effects.

These 2D materials are not only useful as semiconductors, though. Some, such as hexagonal boron nitride, can act as gate dielectrics, having a dielectric constant similar to that of silicon dioxide, which was routinely used for that job until about a decade ago. Add graphene in place of the transistor’s metal parts and you’ve got a combination of 2D materials that forms a complete transistor. Indeed, separate groups of researchers built such devices as far back as 2014. While these prototypes were much larger, you could imagine scaling them down to the size of just a few nanometers.

As amazing as an all-2D transistor that’s a fraction of the size of today’s devices might be, that won’t be the first implementation of 2D materials in electronic circuits. Instead, 2D materials will probably arrive in low-power circuits that have more relaxed performance requirements and area constraints.

The set of circuits we’re targeting at Imec are built in the so-called back-end-of-line. Chipmaking is divided into two parts: the front-end-of-line part consists of processes—many of them requiring high temperatures—that alter the silicon itself, such as implanting dopants to define the parts of a transistor. The back-end-of-line part builds the many layers of interconnects that link the transistors to form circuits and deliver power.

With traditional transistor scaling becoming more and more difficult, engineers have been looking for ways to add functionality to the interconnect layers. You can’t do this simply by using ordinary silicon processes because the heat involved would damage the devices and interconnects beneath them. So, many of these schemes rely on materials that can be made into devices at relatively low temperatures.

A specific advantage of using 2D semiconductors instead of some other candidates is the potential ability to build both p-type (carrying positive charges) and n-type (carrying electrons) devices, a necessity in CMOS logic. CMOS circuits are the backbone of today’s logic because, ideally, they consume power only when switching from one state to the other. In our preferred 2D semiconductor, we’ve demonstrated n-type transistors but not yet p-type. However, the physics underlying these materials strongly suggests we can get there through engineering the dielectrics and metals that contact the semiconductor.

Being able to produce both p– and n-type devices would allow the development of compact back-end logic circuits such as repeaters. Repeaters essentially relay data that must travel relatively far across a chip. Ordinarily, the transistors involved reside on the silicon, but that means signals must climb up the stack of interconnects until they reach a layer where they can travel part of the distance to their destination, then go back down to the silicon to be repeated and up again to the long-distance interconnect layer. It’s a bit like having to exit the highway and drive into the center of a crowded city to buy petrol before getting back on the highway.

A repeater up near the long-distance interconnect layer is more akin to a motorway petrol station. It saves the time it would take the signal to make the two-way vertical trip and also prevents the loss of power due to the resistance of the vertical interconnects. What’s more, moving the repeater to the interconnect layer saves space on the silicon for more logic.

Repeaters aren’t the only potential use. A 2D material could also be used to build other circuits, such as on-chip power-management systems, signal buffers, and memory selectors. One thing these circuits all have in common is that they don’t require the device to drive a lot of current, so one layer of 2D material would probably be sufficient.

Neither future supersmall 2D devices nor the less demanding back-end-of-line circuits will be possible without a fabrication process compatible with industry-standard 300-millimeter silicon wafers. So our team at Imec is working on just that, hoping to develop a process that will serve for all applications.

The first step is identifying the most promising 2D material and device architecture. We have therefore benchmarked a variety of 2D semiconductors and 2D FET architectures against an advanced silicon FinFET device.

Because researchers have the most experience with molybdenum disulfide (MoS2), experimental devices made using it have advanced furthest. Indeed, at the IEEE International Electron Device Meeting last December, Imec unveiled an MoS2 transistor with a channel just 30 nanometers across and source and drain contacts only 13 nm long. But after examining the possibilities, we’ve decided that MoS2 is not the answer. Instead, we concluded that among all the materials compatible with 300-mm silicon-wafer technology, tungsten disulfide (WS2) in the form of a stacked nanosheet device has the highest performance potential, meaning it can drive the most current. For less demanding, back-end-of-line applications, we also concluded that a FET architecture with a gate both below and above the semiconductor channel region works better than one with only a single gate.

We already knew one important thing about WS2 before we reached that conclusion: We can make a high-quality version of it on a 300-mm silicon wafer. We demonstrated that for the first time in 2018 by growing the material on a wafer using metal-organic chemical vapor deposition (MOCVD), a common process that grows crystals on a surface by means of a chemical reaction. The approach we took results in thickness control down to a single-molecule layer, or monolayer, over the full 300-mm wafer. The benefits of the MOCVD growth come, however, at the price of a high temperature—and recall that high temperatures are forbidden in back-end processes because they could damage the silicon devices below.

To get around this problem, we grow the WS2 on a separate wafer and then transfer it to the already partially fabricated silicon wafer. The Imec team developed a unique transfer process that allows a single layer of WS2—as thin as 0.7 nm—to be moved to a silicon target wafer with negligible degradation in the 2D material’s electrical properties.

The process starts by growing the WS2 on an oxide-covered silicon wafer. That’s then placed in contact with a specially prepared wafer. This wafer has a layer of material that melts away when illuminated by a laser. It also has a coating of adhesive. The adhesive side is pressed to the WS2-covered wafer, and the 2D material peels away from the growth wafer and sticks to the adhesive. Then the adhesive wafer with its 2D cargo is flipped over onto the target silicon wafer, which in a real chipmaking effort would already have transistors and several layers of interconnect on it. Next, a laser is shone through the wafer to break the bulk of it away, leaving only the adhesive and the WS2 atop the target wafer. The adhesive is removed with chemicals and plasma. What’s left is just the processed silicon with the WS2 attached to it, held in place by Van der Waals forces.

The process is complicated, but it works. There is, of course, room for improvement, most importantly in mitigating defects caused by unwanted particles on the wafer surface and in eliminating some defects that occur at the edges.

Once the 2D semiconductor has been deposited, building devices can begin. On that front there have been triumphs, but some major challenges remain.

Perhaps the most crucial issue to tackle is the creation of defects in the WS2. Imperfections profoundly degrade the performance of a 2D device. In ordinary silicon devices, charge can get caught in imperfections at the interface between the gate dielectric and the channel region. These can scatter electrons or holes near the interface as they try to move through the device, slowing things down. With 2D semiconductors the scattering problem is more pronounced because the interface is the channel.

Sulfur vacancies are the most common defects that affect device channel regions. Imec is investigating how different plasma treatments might make those vacancies less chemically reactive and therefore less prone to alter the transistor’s behavior. We also need to prevent more defects from forming after we’ve grown the monolayer. WS2 and other 2D materials are known to age quickly and degrade further if already defective. Oxygen attacking a sulfur vacancy can cause more vacancies nearby, making the defect area grow larger and larger. But we’ve found that storing the samples in an inert environment makes a difference in preventing that spread.

Defects in the semiconductor aren’t the only problems we’ve encountered trying to make 2D devices. Depositing insulating materials on top of the 2D surface to form the gate dielectric is a true challenge. WS2 and similar materials lack dangling bonds that would otherwise help fasten the dielectric to the surface.

Our team is currently exploring two routes that might help: One is atomic layer deposition (ALD) at a reduced growth temperature. In ALD, a gaseous molecule adsorbs to the semiconductor’s exposed surface to form a single layer. Then a second gas is added, reacting with the adsorbed first one to leave an atomically precise layer of material, such as the dielectric hafnium dioxide. Doing this at a reduced temperature increases the ability of the gas molecules to stick to the surface of the WS2 even when no chemical bonds are available.

The other option is to enhance ALD by using a very thin oxidized layer, such as silicon oxide, to help nucleate the growth of the ALD layer. A very thin layer of silicon is deposited by a physical deposition method such as sputtering or evaporation; it’s then oxidized before a regular ALD deposition of gate oxide is done. We’ve achieved particularly good results with evaporation.

A further challenge in making superior 2D devices is in choosing the right metals to use as source and drain contacts. Metals can alter the characteristics of the device, depending on their work function. That parameter, the minimum energy needed to extract an electron from the metal, can mean the difference between a contact that can easily inject electrons and one that can inject holes. So the Imec team has screened a variety of metals to put in contact with the WS2 nanosheet. We found that the highest on-current in an n-type device was obtained using a magnesium contact, but other metals such as nickel or tungsten work well. We’ll be searching for a different metal for future p-type devices.

Despite these challenges, we’ve been able to estimate the upper limits of device performance, and we’ve mapped out what roads to follow to get there.

As a benchmark, the Imec team used dual-gated devices like those we described earlier. We built them with small, naturally exfoliated flakes of WS2, which have fewer defects than wafer-scale semiconductors. For these lab-scale devices, we were able to measure electron mobility values up to a few hundred square centimeters per volt-second, which nearly matches crystalline silicon and is close to the theoretically predicted maximum for the 2D material. Because this excellent mobility can be found in natural material, we are confident that it should also be possible to get there with materials synthesized on 300-mm wafers, which currently reach just a few square centimeters per volt-second.

For some of the main challenges ahead in 2D semiconductor development, our team has a clear view of the solutions. We know, for example, how to grow and transfer the material onto a 300-mm target wafer; we’ve got an idea of how to integrate the crucial gate dielectric; and we’re on a path to boost the mobility of charge carriers in devices toward a level that could compare with silicon.

But, as we’ve laid out, there are still significant problems remaining. These will require an intensive engineering effort and an even better fundamental understanding of this new class of intriguing 2D materials. Solving these challenges will enable high-performance devices that are scaled down to atomic layers, but they might first bring new capabilities that need less demanding specifications even as we continue to scale down silicon.

This article appears in the February 2020 print issue as “Atom-Thick Transistors.”

About the Author

Iuliana Radu is program director at Imec, in Leuven, Belgium, where she leads the research center’s Beyond CMOs program and quantum computing activities.

Holding Light (Temporarily) in Place

Post Syndicated from Mark Anderson original https://spectrum.ieee.org/tech-talk/semiconductors/optoelectronics/holding-light-temporarily-in-place

Storing light beams—putting an ensemble of photons, traveling through a specially prepared material, into a virtual standstill—has come a step closer to reality with a new discovery involving microwaves.

The research finds that microwaves traveling through a particular configuration of ceramic aluminum oxide rods can be made to hold in place for several microseconds. If the optical or infrared equivalent of this technology can be fabricated, then Internet and computer communications networks (each carried by optical and infrared laser pulses) might gain a new versatile tool that enables temporary, stationary storage of a packet of photons.

Ferroelectric Semiconductors Could Mix Memory and Logic

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/nanoclast/semiconductors/materials/ferroelectric-semiconductors-could-mix-memory-and-logic

Engineers at Purdue University and at Georgia Tech have constructed the first devices from a new kind of two-dimensional material that combines memory-retaining properties and semiconductor properties. The engineers used a newly discovered ferroelectric semiconductor, alpha indium selenide, in two applications: as the basis of a type of transistor that stores memory as the amount of amplification it produces; and in a two-terminal device that could act as a component in future brain-inspired computers. The latter device was unveiled last month at the IEEE International Electron Devices Meeting in San Francisco.

Ferroelectric materials become polarized in an electric field and retain that polarization even after the field has been removed. Ferroelectric RAM cells in commercial memory chips use the former ability to store data in a capacitor-like structure. Recently, researchers have been trying to coax more tricks from these ferroelectric materials by bringing them into the transistor structure itself or by building other types of devices from them.

In particular, they’ve been embedding ferroelectric materials into a transistor’s gate dielectric, the thin layer that separates the electrode responsible for turning the transistor on and off from the channel through which current flows. Researchers have also been seeking a ferroelectric equivalent of the memristors, or resistive RAM, two-terminal devices that store data as resistance. Such devices, called ferroelectric tunnel junctions, are particularly attractive because they could be made into a very dense memory configuration called a cross-bar array. Many researchers working on neuromorphic- and low-power AI chips use memristors to act as the neural synapses in their networks. But so far, ferroelectric tunnel junction memories have been a problem.

“It’s very difficult to do,” says IEEE Fellow Peide Ye, who led the research at Purdue University. Because traditional ferroelectric materials are insulators, when the device is scaled down, there’s too little current passing through, explains Ye. When researchers try to solve that problem by making the ferroelectric layer very thin, the layer loses its ferroelectric properties.  

Instead, Ye’s group sought to solve the conductance problem by using a new ferroelectric material—alpha indium selenide— that acts as a semiconductor instead of an insulator. Under the influence of an electric field, the molecule undergoes a structural change that holds the polarization. Even better, the material is ferroelectric even as a single-molecule layer that is only about a nanometer thick. “This material is very unique,” says Ye.

Ye’s group made both transistors and memristor-like devices using the semiconductor. The memristor-like device, which they called a ferroelectric-semiconductor junction (FSJ), is just the semiconductor sandwiched between two conductors. This simple configuration could be formed into a dense cross-bar array and potentially shrunk down so that each device is only about 10 nanometers across, says Ye.

Proving the ability to scale the device down is the next goal for the research, along with characterizing how quickly the devices can switch, explains Ye. Further on, his team will look at applications for the FSJ in neuromorphic chips, where researchers have been trying a variety of new devices in the search for the perfect artificial neural synapse.

Diode Lasers Jump to the Deep Ultraviolet

Post Syndicated from Jeff Hecht original https://spectrum.ieee.org/tech-talk/semiconductors/optoelectronics/diode-lasers-jump-to-the-deep-ultraviolet

The first electrically powered semiconductor laser emitting in the deep ultraviolet marks a big step into a new field, says Ramón Collazo, a materials science professor at North Carolina State University and a founder of Adroit Materials in Cary, NC.

Researchers had thought “there was a hard wall” blocking diode lasers from emitting ultraviolet light shorter than 315 nm even in laboratory lasers, Collazo says. Now a team including Hiroshi Amano of Nagoya University, who shared the 2014 Nobel Physics Prize for inventing efficient blue light-emitting diodes, has scored another breakthrough by demonstrating a 271.8-nm diode laser, more than 40 nm deeper into the ultraviolet.

“Bio-sensing and sterilization are expected to be the first key applications” of deep ultraviolet diode lasers, says Ziyi Zhang of the Asahi Kasei Corporate Research Center in Fuji, lead author of a paper coauthored by Amano. Bio-sensors based on diode lasers “could be far smaller, cheaper, and more easily replaceable” than the bulky gas lasers, which are now the only type available at wavelengths shorter than 300 nm, Zhang says.

The U.S. Pentagon had made a significant investment in developing deep-ultraviolet lasers for bio-sensing, says Collazo, but “after three DARPA programs, the Japanese got it,” he said with a chuckle. He says that demonstrating a deep-ultraviolet laser opens the door to making diode lasers across a broad range from 220 to 365 nm.

Commercial LEDs made of the same compound, aluminum-gallium nitride, can emit wavelengths as short as 210 nm. However, their light spreads rapidly, leaving little power after tens of centimeters, which limits their applications. Laser diodes concentrate their beam over a longer distance, delivering higher power to small spots, and their light is concentrated in a band of less than 1 nm, compared to more than 10 nm for LEDs. “These features of laser diodes should enable some medical applications,” says Zhang.

Diode lasers are much harder to make than LEDs because they require passing higher current densities through the layer where current carriers combine to emit light. This is a particular problem for the nitride compounds that emit in the blue, violet and ultraviolet because they are prone to crystalline defects that can cause failures at high current densities. Such material problems had stalled progress in blue LEDs and diode lasers until Amano and Isamu Akasaki at Nagoya University and Shiju Nakamura, then at the Nichia Corporation, developed new ways of processing the mixture of gallium, indium and nitrogen needed for blue emission in the early 1990s. They succeeded first with LEDs and later with diode lasers at the 405-nm wavelength needed to store high-definition digital video on Blu-Ray discs.

Diodes made from gallium, indium and nitrogen emit blue light, with the wavelength decreasing as the indium content decreases, reaching about 370 nm from pure GaN. Aluminum must be added to replace some gallium to reach shorter wavelengths, but adding aluminum also makes the compound more vulnerable to defects. That’s not a severe problem for LEDs, which reached 210 nanometers in the deep ultraviolet in 2006. However, the high current density in diode lasers stalled their development in the ultraviolet. The shortest wavelengths in commercial diodes remain 375 nm, and short-lived laboratory versions remained stalled around 320 nm for years. 

In 2018, a team from North Carolina State and Adroit Materials (Cary, NC) led by Adroit chief operating office Ronny Kirste was able to reduce defect levels in AlGaN containing more aluminum than gallium to produce laser light at 265 nm in the deep ultraviolet.  However, their semiconductor lasers were powered by 193-nm light from a large pulsed gas laser, a technique useful in research, but not practical for applications. The holy grail for practical deep ultraviolet lasers is powering them directly by electrical current passing through the semiconductor.

A team from Asahi Kasei Corporate Research & Development in Fuji, Nagoya, and Crystal IS in Green Island, NY demonstrated the new electrically powered diode laser emitting at 271.8 nm.  The keys to their success, Zhang says, were design of the laser diode structure, their technique for doping the semiconductor, and epitaxial growth on a substrate of single-crystal AlN, which reduced threshold current and operating voltage. Layers in the structure contained up to twice as much aluminum as gallium.

Their laser generated 50-nanosecond pulses at a rate of 2000 Hz, but most applications are expected to require a continuous laser beam. Zhang says that further reductions in threshold current and operating voltage should allow continuous-wave operation. Asahi Kasei plans to continue teaming the Nagoya to improve their understanding of the material system and develop commercial versions.

Adroit Materials had already working on AlGaN, and now is working to duplicate the Asahi Kasei results. “We want to replace those gas lasers” which have long been the only laser sources practical for most short-wavelength ultraviolet applications, says Kirste. “The market is huge for that.”  Much of that market is biological because DNA absorbs strongly at 260 nm. In addition to sensing biological material including potential pathogen, bright deep-ultraviolet sources can break apart DNA, killing pathogens. UV LEDs emitting in that range already can sterilize small volumes of water, such as needed by soldiers in the field where water supplies are suspect. Compact laser sources could sterilize larger volumes quicker.

Cerebras’s Giant Chip Will Smash Deep Learning’s Speed Barrier

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/semiconductors/processors/cerebrass-giant-chip-will-smash-deep-learnings-speed-barrier

graphic link to special report landing page

Artificial intelligence today is much less than it could be, according to Andrew Feldman, CEO and cofounder of AI computer startup Cerebras Systems.

The problem, as he and his fellow Cerebras founders see it, is that today’s artificial neural networks are too time-consuming and compute-intensive to train. For, say, a self-driving car to recognize all the important objects it will encounter on the road, the car’s neural network has to be shown many, many images of all those things. That process happens in a data center where computers consuming tens or sometimes hundreds of kilowatts are dedicated to what is too often a weeks-long task. Assuming the resulting network can carry out the task with the needed accuracy, the many coefficients that define the strength of connections in the network are then downloaded to the car’s computer, which performs the other half of deep learning, called inference.

Cerebras’s customers—and it already has some, despite emerging from stealth mode only this past summer—complain that training runs for big neural networks on today’s computers can take as long as six weeks. At that rate, they are able to train only maybe six neural networks in a year. “The idea is to test more ideas,” says Feldman. “If you can [train a network] instead in 2 or 3 hours, you can run thousands of ideas.”

When IEEE Spectrum visited Cerebras’s headquarters in Los Altos, Calif., those customers and some potential new ones were already pouring their training data into four CS-1 computers through orange-jacketed fiber-optic cables. These 64-centimeter-tall machines churned away, while the heat exhaust of the 20 kilowatts being consumed by each blew out into the Silicon Valley streets through a hole cut into the wall.

The CS-1 computers themselves weren’t much to look at from the outside. Indeed, about three-quarters of each chassis is taken up with the cooling system. What’s inside that last quarter is the real revolution: a hugely powerful computer made up almost entirely of a single chip. But that one chip extends over 46,255 square millimeters—more than 50 times the size of any other processor chip you can buy. With 1.2 trillion transistors, 400,000 processor cores, 18 gigabytes of SRAM, and interconnects capable of moving 100 million billion bits per second, Cerebras’s Wafer Scale Engine (WSE) defies easy comparison with other systems.

The statistics Cerebras quotes are pretty astounding. According to the company, a 10-rack TPU2 cluster—the second of what are now three generations of Google AI computers—consumes five times as much power and takes up 30 times as much space to deliver just one-third of the performance of a single computer with the WSE. Whether a single massive chip is really the answer the AI community has been waiting for should start to become clear this year. “The [neural-network] models are becoming more complex,” says Mike Demler, a senior analyst with the Linley Group, in Mountain View, Calif. “Being able to quickly train or retrain is really important.”

Customers such as supercomputing giant Argonne National Laboratory, near Chicago, already have the machines on their premises, and if Cerebras’s conjecture is true, the number of neural networks doing amazing things will explode.

When the founders of Cerebras—veterans of Sea Micro, a server business acquired by AMD—began meeting in 2015, they wanted to build a computer that perfectly fit the nature of modern AI workloads, explains Feldman. Those workloads are defined by a few things: They need to move a lot of data quickly, they need memory that is close to the processing core, and those cores don’t need to work on data that other cores are crunching.

This suggested a few things immediately to the company’s veteran computer architects, including Gary Lauterbach, its chief technical officer. First, they could use thousands and thousands of small cores designed to do the relevant neural-network computations, as opposed to fewer more general-purpose cores. Second, those cores should be linked together with an interconnect scheme that moves data quickly and at low energy. And finally, all the needed data should be on the processor chip, not in separate memory chips.

The need to move data to and from these cores was, in large part, what led to the WSE’s uniqueness. The fastest, lowest-energy way to move data between two cores is to have them on the same silicon substrate. The moment data has to travel from one chip to another, there’s a huge cost in speed and power because distances are longer and the “wires” that carry the signals must be wider and less densely packed.

The drive to keep all communications on silicon, coupled with the desire for small cores and local memory, all pointed to making as big a chip as possible, maybe one as big as a whole silicon wafer. “It wasn’t obvious we could do that, that’s for sure,” says Feldman. But “it was fairly obvious that there were big benefits.”

For decades, engineers had assumed that a wafer-scale chip was a dead end. After all, no less a luminary than the late Gene Amdahl, chief architect of the IBM System/360 mainframe, had tried and failed spectacularly at it with a company called Trilogy Systems. But Lauterbach and Feldman say that any comparison with Amdahl’s attempt is laughably out-of-date. The wafers Amdahl was working with were one-tenth the size of today’s, and features that made up devices on those wafers were 30 times the size of today’s.

More important, Trilogy had no way of handling the inevitable errors that arise in chip manufacturing. Everything else being equal, the likelihood of there being a defect increases as the chip gets larger. If your chip is nearly the size of a sheet of letter-size paper, then you’re pretty much asking for it to have defects.

But Lauterbach saw an architectural solution: Because the workload they were targeting favors having thousands of small, identical cores, it was possible to fit in enough redundant cores to account for the defect-induced failure of even 1 percent of them and still have a very powerful, very large chip.

Of course, Cerebras still had to solve a host of manufacturing issues to build its defect-tolerant giganto chip. For example, photolithography tools are designed to cast their feature-defining patterns onto relatively small rectangles, and to do that over and over. That limitation alone would keep a lot of systems from being built on a single wafer, because of the cost and difficulty of casting different patterns in different places on the wafer.

But the WSE doesn’t require that. It resembles a typical wafer full of the exact same chips, just as you’d ordinarily manufacture. The big challenge was finding a way to link those pseudochips together. Chipmakers leave narrow edges of blank silicon called scribe lines around each chip. The wafer is typically diced up along those lines. Cerebras worked with Taiwan Semiconductor Manufacturing Co. (TSMC) to develop a way to build interconnects across the scribe lines so that the cores in each pseudochip could communicate.

With all communications and memory now on a single slice of silicon, data could zip around unimpeded, producing a core-to-core bandwidth of 1,000 petabits per second and an SRAM-to-core bandwidth of 9 petabytes per second. “It’s not just a little more,” says Feldman. “It’s four orders of magnitude greater bandwidth, because we stay on silicon.”

Scribe-line-crossing interconnects weren’t the only invention needed. Chip-manufacturing hardware had to be modified. Even the software for electronic design automation had to be customized for working on such a big chip. “Every rule and every tool and every manufacturing device was designed to pick up a normal-sized chocolate chip cookie, and [we] delivered something the size of the whole cookie sheet,” says Feldman. “Every single step of the way, we have to invent.”

Wafer-scale integration “has been dismissed for the last 40 years, but of course, it was going to happen sometime,” he says. Now that Cerebras has done it, the door may be open to others. “We think others will seek to partner with us to solve problems outside of AI.”

Indeed, engineers at the University of Illinois and the University of California, Los Angeles, see Cerebras’s chip as a boost to their own wafer-scale computing efforts using a technology called silicon-interconnect fabric [see “Goodbye, Motherboard. Hello, Silicon-Interconnect Fabric,” IEEE Spectrum, October 2019]. “This is a huge validation of the research we’ve been doing,” says the University of Illinois’s Rakesh Kumar. “We like the fact that there is commercial interest in something like this.”

The CS-1 is more than just the WSE chip, of course, but it’s not much more. That’s both by design and necessity. What passes for the motherboard is a power-delivery system that sits above the chip and a water-cooled cold plate below it. Surprisingly enough, it was the power-delivery system that was the biggest challenge in the computer’s development.

The WSE’s 1.2 trillion transistors are designed to operate at about 0.8 volts, pretty standard for a processor. There are so many of them, though, that in all they need 20,000 amperes of current. “Getting 20,000 amps into the wafer without significant voltage drop is quite an engineering challenge—much harder than cooling it or addressing the yield problems,” says Lauterbach.

Power can’t be delivered from the edge of the WSE, because the resistance in the interconnects would drop the voltage to zero long before it reached the middle of the chip. The answer was to deliver it vertically from above. Cerebras designed a fiberglass circuit board holding hundreds of special-purpose chips for power control. One million copper posts bridge the millimeter or so from the fiberglass board to points on the WSE.

Delivering power in this way might seem straightforward, but it isn’t. In operation, the chip, the circuit board, and the cold plate all warm up to the same temperature, but they expand when doing so by different amounts. Copper expands the most, silicon the least, and the fiberglass somewhere in between. Mismatches like this are a headache in normal-size chips because the change can be enough to shear away their connection to a printed circuit board or produce enough stress to break the chip. For a chip the size of the WSE, even a small percentage change in size translates to millimeters.

“The challenge of [coefficient of thermal expansion] mismatch with the motherboard was a brutal problem,” says Lauterbach. Cerebras searched for a material with the right intermediate coefficient of thermal expansion, something between those of silicon and fiberglass. Only that would keep the million power-delivery posts connected. But in the end, the engineers had to invent one themselves, an endeavor that took a year and a half to accomplish.

The WSE is obviously bigger than competing chips commonly used for neural-network calculations, like the Nvidia Tesla V100 graphics processing unit or Google’s Tensor Processing Unit. But is it better?

In 2018, Google, Baidu, and some top academic groups began working on benchmarks that would allow apples-to-apples comparisons among systems. The result, MLPerf, released training benchmarks in May 2018.

According to those benchmarks, the technology for training neural networks has made some huge strides in the last few years. On the ResNet-50 image-classification problem, the Nvidia DGX SuperPOD—essentially a 1,500-GPU supercomputer—finished in 80 seconds. It took 8 hours on Nvidia’s DGX-1 machine (circa 2017) and 25 days using the company’s K80 from 2015.

Cerebras hasn’t released MLPerf results or any other independently verifiable apples-to-apples comparisons. Instead the company prefers to let customers try out the CS-1 using their own neural networks and data.

This approach is not unusual, according to analysts. “Everybody runs their own models that they developed for their own business,” says Karl Freund, an AI analyst at Moor Insights. “That’s the only thing that matters to buyers.”

Early customer Argonne National Labs, for one, has some pretty intense needs. In training a neural network to recognize, in real time, different types of gravitational-wave events, scientists recently used one-quarter of the resources of Argonne’s megawatt-consuming Theta supercomputer, the 28th most powerful system in the world.

Cutting power consumption down to mere kilowatts seems like a key benefit in supercomputing. Unfortunately, Lauterbach doubts that this feature will be much of a selling point in data centers. “While a lot of data centers talk about [conserving] power, when it comes down to it…they don’t care,” he says. “They want performance.” And that’s something a processor nearly the size of a dinner plate can certainly provide.

This article appears in the January 2020 print issue as “Huge Chip Smashes Deep Learning’s Speed Barrier.”

Arm Shows Backside Power Delivery as Path to Further Moore’s Law

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/nanoclast/semiconductors/design/arm-shows-backside-power-delivery-as-path-to-further-moores-law

People often think that Moore’s Law is all about making smaller and smaller transistors. But these days, a lot of the difficulty is squeezing in the tangle of interconnects needed to get signals and power to them. Those smaller, more dense interconnects are more resistive, leading to a potential waste of power. At the IEEE International Electron Devices Meeting in December, Arm engineers presented a processor design that demonstrates a way to reduce the density of interconnects and deliver power to chips with less waste.

Tips and Tricks on how to verify control loop stability

Post Syndicated from IEEE Spectrum Recent Content full text original https://spectrum.ieee.org/whitepaper/tips-and-tricks-on-how-to-verify-control-loop-stability

The Application Note explains the main measurement concept and will guide the user during the measurements and mention the main topics in a practical manner. Wherever possible, a hint is given where the user should pay attention.

Register for our Application Note "Tips and Tricks on how to verify control loop stability"

TSMC’s 5-Nanometer Process on Track for First Half of 2020

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/nanoclast/semiconductors/devices/tsmc-5-nanometer-process

“Those who know, know.” That was all that TSMC senior director of advanced technology Geoffrey Yeap would say about the mystery ingredient that helps boost the performance of devices made using the company’s next generation manufacturing process. N5, TSMC’s 5-nanometer process, is on track for high-volume production during the first half of 2020, Yeap told engineers at the IEEE International Electron Device Meeting in San Francisco, Wednesday.

Compared with the company’s 7-nanometer process, used to make iPhone X processors among other high-end systems, N5 leads to devices that are 15 percent faster and 30 percent more power efficient. It produces logic that is 1.84 times as small as the previous process and produces SRAM cells that are only 0.021 square micrometers, the most compact ever reported, Yeap said.

The process is currently in what’s called risk production—initial customers are taking a risk that it will work for their designs. Yeap reported that initial average SRAM yield was about 80 percent and that yield improvement has been faster for N5 than any other recent process introduction.

Some of that yield improvement is likely due to the use of extreme ultraviolet lithography (EUV). N5 is the first TSMC process designed around EUV. The previous generation was developed first using the established 193-nanometer immersion lithography first, and then when EUV was introduced, some of the most difficult to produce chip features were made with the new technology. Because it uses a 13.5-nanometer light instead of 193-nanometers, EUV can define chip features in one step—compared with three or more steps using 193-nanometer light. With more than 10 EUV layers, N5 is the first new process “in quite a long time” that uses fewer photolithography masks than its predecessor, Yeap said.

Part of the performance enhancement comes from the inclusion, for the first time in TSMC’s process, of a “high-mobility channel”. Charge carrier mobility is the speed with which current moves through the transistor, and therefore limits how quickly the device can switch. Asked (several times) about the makeup of the high-mobility channel, Yeap declined to offer details. “Those who know, know,” he said, prompting laughter from the audience. TSMC and others have explored germanium-based channels in the past. And earlier in the day, Intel showed a 3D process with silicon NMOS on the bottom and a layer of germanium PMOS above it.

Yeap would not even be tied down on which type of transistor, NMOS or PMOS or both, had the enhanced channel. However, the latter is probably not very mysterious. Holes generally travel more slowly through silicon devices than electrons and therefore the PMOS devices would benefit from enhanced mobility. When pressed Yeap confirmed that only one variety of device had the high-mobility channel.

Photonics Meets Plasmonics in New Switch that Could Steer Lidar Laser Beams

Post Syndicated from Jeff Hecht original https://spectrum.ieee.org/tech-talk/semiconductors/optoelectronics/new-electro-mechanical-switch-integrated-photonics

The synergy of electronic processing and optical communications has powered the decades-long boom in information technology. But the need to convert signals back and forth between electrical and optical forms is becoming a bottleneck for the emerging field of integrated photonics.

A new type of switch that combines electrical and mechanical effects to redirect light could open the door to large-scale reconfigurable photonic networks for several applications including beam steering for lidars and optical neural networks for computing. 

Currently, integrated photonics are used in high-performance fiber-optic systems , and a joint government-industry program called AIM Photonics is pushing their manufacture. However, current optical switches are too big and require too much power to blend well into integrated photonics. The new hybrid nano-opto-electro-mechanical switch has a footprint of 10 square micrometers and runs on only one volt—making it compatible with the CMOS (complementary metal-oxide-semiconductor) silicon electronics used in integrated photonics, says Christian Haffner from the Swiss Federal Institute of Technology in Zurich now working at the National Institute for Standards and Technology (NIST) in Gaithersburg, Maryland and the researcher who led the team that developed it.

The root of the problem Haffner set out to solve is that photons and electrons behave very differently.

Photons are great for communications because they travel at the speed of light and interact weakly with each other and matter, but they are much larger than chip features and require high voltages to redirect them because of their weak interactions.

Electrons are much smaller and interact much more strongly than photons, making them better for switching and for processing signals. However, electrons move slower than light, and more energy is needed to move them.

Long-distance communication systems process signals electronically and convert the signal into light for transmission, but converting between signal formats is cumbersome for local transmission. The new switch makes it possible to redirect optical signals on the integrated photonic circuit without having to convert them to electrical format and then back to optical format for further transmission. 

In Science, Haffner and colleagues describe a hybrid nano-opto-electro-mechanical switch that would occupy only about 10 square micrometers on an integrated photonic circuit. Their switch is a small multilayered disk sitting at a T-junction between two optical waveguides—stripes of transparent silica that guide light—that meet at a right angle. The top layer of the disk is a four-micrometer circle of 40-nanometer gold membrane resting on a small piece of alumina on layer of silicon deposited on silica. That structure acts as a curved waveguide resonant with both the input and output waveguides, so it can transfer resonant light between the two. 

Light within the silica waveguides remains as photons, but within the switch the light excites oscillations of surface electrons in the gold, producing plasmons that vibrate at the frequency of the light wave but over a light much smaller than the optical wavelength. That tight confinement of the plasmonic part of the energy in the air gap between the gold and silicon creates a strong opto-electro-mechanical effect concentrated in the small volume of the switch. 

With no voltage applied to the switch, the plasmonic waveguide remains resonant with the silica waveguides, so it couples light from the input waveguide to the output waveguide with minimal loss, as shown in the animation.

Applying one volt to the switch produces a static charge that pulls the gold membrane toward the silicon layer, changing the shape of the waveguide in the switch so it shifts the phase of the light by 180 degrees. This causes destructive interference in the switch, breaking the resonance and the coupling of light into the side waveguide, so the light instead continues through the input waveguide to another switch.

“What we have in the end,” says Haffner, “is a hybrid [switch], partly photonic and partly plasmonic, that manipulates light very efficiently.” The plasmonic part concentrates the switching in a small area; the photonic part experiences low loss. Applying a one-volt bias compatible with CMOS electronics across such a short distance can produce a very strong force. That gives the switch a small footprint, low loss, and lower power consumption, which conventional electro-optic switches cannot achieve simultaneously.

Mass of the gold film is so low that the switch can operate millions of times a second. That’s adequate for most switching, says Haffner, but it does have limits. The mechanical part of the switch cannot reach the picosecond speeds needed to modulate light in an optical transmitter. 

The first applications are likely to be in laser beam steering for lidar, particularly for autonomous vehicles where continual information on the local environment is vital for safety. Another potential application is optical routing of signals on integrated photonic chips to create optical neural networks for deep-learning applications. The switch can redirect signals millions of times a second, a time scale needed by such applications.

“I don’t see any issues in fabricating [the switches] with high yield,” says Haffner. 

How to Reduce the Bill of Material Costs with Digital Signal Processing

Post Syndicated from IEEE Spectrum Recent Content full text original https://spectrum.ieee.org/whitepaper/how-to-reduce-the-bill-of-material-costs-with-digital-signal-processing

The need to decrease the bill of material (BOM) costs in embedded products is being driven by the need for high volume, low-cost sensor systems. As IoT devices become more sophisticated, they require developers to utilize digital signal processing (DSP) to handle more features within the product, such as device provisioning.

In this paper, we will examine how DSP can be used to reduce a product’s cost.

You will learn:

  • The technology trends moving data processing to the edge of the network to enable more compute performance
  • The benefits of digital signal processing, including decreased product dimensions, product flexibility, shorter design cycle, and in-field adaptability
  • How to convert analog circuits to software using modeling software such as MathWorks MATLAB or Advanced Solutions Nederlands (ASN) filter designer
  • How to select the right DSP processor solution to benefit from reduced BOM costs
  • The capabilities and features of the Arm Cortex-M processors with DSP extensions to help you get your signal processing application running as quickly as possible.

Artificial Intelligence in Software Defined SIGINT Systems

Post Syndicated from IEEE Spectrum Recent Content full text original https://spectrum.ieee.org/whitepaper/artificial-intelligence-in-software-defined-sigint-systems

As wireless protocols grow more complex, spectrum environments become more contested and electronic warfare increases in sophistication.

Read how you can combine artificial intelligence and deep learning with commercial off-the-shelf software-defined radio hardware to train algorithms.

You can teach them to detect new threats faster, reduce development risk and support burden, and deploy in signals intelligence and spectrum monitoring scenarios limited by SWaP (size, weight, and power). 

U.S. Invests in Fabs That Make Radiation-Hardened Chips

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/tech-talk/semiconductors/devices/us-invests-in-radiationhardenedchip-fabs

The U.S. is investing in upgrades to the fabrication facility that makes the radiation-hardened chips for its nuclear arsenal. It is also spending up to US $170-million to enhance the capabilities of SkyWater Technology Foundry, in Bloomington, Minn., in part to improve the company’s radiation-hardened-chip line for other Defense Department needs.

A Simple Filter Turns Blue OLED Light Into White

Post Syndicated from XiaoZhi Lim original https://spectrum.ieee.org/tech-talk/semiconductors/optoelectronics/a-simple-filter-makes-blueemitting-oleds-give-off-white-light

Organic light-emitting diodes (OLEDs) have come a long way since the first working device was reported three decades ago. Prized for their dark blacks, crisp image reproduction, and power efficiency, today’s OLEDs dominate the screens of Android phones and LG televisions. They may take over iPhones as early as next year.

And because OLEDs are cheap and easy to make, we ought to also use them to make white light for general illumination, says Konstantinos Daskalakis, a post-doctoral researcher at Aalto University in Finland.

Except white is an OLED’s Achilles’ heel. Typically, to get white light, individual red, green, and blue emitters shine at the same time. This makes white the most power-hungry color, reportedly requiring six times as much power as it takes to produce the color black on a Google Pixel. Other strategies to generate white light include carefully doping emitting layers with chemicals, but this approach makes it harder to fabricate devices.

In a proof-of-concept experiment, Daskalakis and his supervisor Paivi Torma converted conventional blue-emitting OLEDs to white-emitting ones simply by depositing a distributed Bragg reflector (DBR)—a stack of two alternating materials with high and low refractive indexes—on top of the OLEDs.

Wanted: A Bomb Detector as Sensitive as a Dog’s Nose

Post Syndicated from Michelle Hampson original https://spectrum.ieee.org/tech-talk/semiconductors/devices/using-a-twopronged-approach-to-detect-explosive-substances-from-bombs

If a suicide bomber lurks in the public with an explosive device, bomb-sniffing dogs can often detect the explosive chemicals from the tiniest whiff—these canine superheroes can sense the presence of the explosive triacetone triperoxide (TATP) if just a few molecules are present, on the scale of parts per trillion.

Researchers at the University of Rhode Island are striving to make a comparable device for detecting TATP in its vapor form. Their new detection system, which pairs a conductance sensor with a traditional thermodynamic sensor, confirms the presence of TATP at the level of parts per billion (ppb). Their work is described in a study published on 2 October in IEEE Sensors Letters.

Forget Moore’s Law—Chipmakers Are More Worried About Heat and Power Issues

Post Syndicated from Tekla S. Perry original https://spectrum.ieee.org/view-from-the-valley/semiconductors/design/power-problems-might-drive-chip-specialization

Power consumption and heat generation: these hurdles impede progress toward faster, cheaper chips, and are worrying semiconductor industry veterans far more than the slowing of Moore’s Law. That was the takeaway from several discussions about current and future chip technologies held in Silicon Valley this week.

John Hennessy—president emeritus of Stanford University, Google chairman, and MIPS Computer Systems founder—says Moore’s Law “was an ambition, a goal. It wasn’t a law; it was something to shoot for.”

U.S. Semiconductor Industry Veterans Keep Wary Eyes on China

Post Syndicated from Tekla S. Perry original https://spectrum.ieee.org/view-from-the-valley/semiconductors/devices/semiconductor-industry-veterans-keep-wary-eyes-on-china

How might the U.S. chip industry solve a problem like China?

A panel of semiconductor industry veterans took up this question at a Churchill Club event this week. The group generally expressed worry about the impact China will have on the future of the U.S. chip industry, and the lack of good ideas about how the U.S. industry can respond to threats posed by China.

“China is the ultimate conundrum,” says Stanford president emeritus and MIPS Computer Systems founder John Hennessy. “It’s a large market that U.S. companies need access to, together with being what will become a major technical competitor. We have never faced that.”

The consolidation of silicon manufacturing into two main foundries raises the threat level, pointed out Diane Bryant, former Intel and Google Cloud executive.

“You really just have TSMC and Samsung left,” she said. “And TSMC is in Taiwan, so you have to be thinking about China and the threat to Taiwan, and what will happen to TSMC.”

China will take over Taiwan “the same time North Korea takes over South Korea,” quipped Hennessy, giving it control over most of the world’s semiconductor manufacturing capabilities.

“What do you do tomorrow if TSMC and Samsung are off limits?” he asked his fellow panel members.

“You can’t go to Global Foundries,” which indeed has some U.S. semiconductor manufacturing capability, said Bryant, “unless you really want Moore’s Law to be dead.” (Global Foundries recently stopped developing the most advanced semiconductor processes.) 

Rodrigo Liang, CEO of SambaNova Systems, argued that fixing this problem can only be done at the level of the U.S. government.

Pradeep Sindhu, founder of Juniper Networks and founder and CEO of Fungible, agreed. “The U.S. government needs an industrial policy,” he said, “and it doesn’t have one.”

The foundry issue is a long-term problem. Perhaps a nearer term question is how the growing capability of China’s tech industry will impact U.S.-based companies.

“China is talking about becoming tech independent, becoming net exporters,” said Bryant. “We can talk about how many years [it will take], but it is inevitable.”

Companies in China will catch up for several reasons, panelists indicated. For one, said Sindhu, they are very hungry to learn.

For another, said Navin Chaddha, managing director of the Mayfield Fund, China’s huge market gives Chinese companies a boost. “Usually innovation happens when you are close to a market,” he said. To date, the U.S. companies and Samsung have benefitted from the boom” in the Chinese tech market, but now “we are seeing Chinese companies benefitting from their local market… and China is the biggest market when it comes to broadband users.”

A solution?

“Invest in that market,” says Chaddha.

That strategy is not without pitfalls, Hennessy indicated. “What happens to your technology when you ship it over there?” he asked.

“To the extent that we can protect it, we will,” Sindhu said.

Hennessy remained skeptical. “Just wait until you sign the deal and send it over,” he said.

“This isn’t a redo of semiconductor wars with Japan in the 80s,” he concluded.  “This is a country that has scale, that has entrepreneurial zeal. They will give us a run for the money.”

Next-Gen AR Glasses Will Require New Chip Designs

Post Syndicated from Tekla S. Perry original https://spectrum.ieee.org/view-from-the-valley/semiconductors/design/dramatic-changes-in-chip-design-will-be-necessary-to-make-ar-glasses-a-reality

What seems like a simple task—building a useful form of augmented reality into comfortable, reasonably stylish, eyeglasses—is going to need significant technology advances on many fronts, including displays, graphics, gesture tracking, and low-power processor design.

That was the message of Sha Rabii, Facebook’s head of silicon and technology engineering. Rabii, speaking at Arm TechCon 2019 in San Jose, Calif., on Tuesday, described a future with AR glasses that enable wearers to see at night, improve overall eyesight, translate signs on the fly, prompt wearers with the names of people they meet, create shared whiteboards, encourage healthy food choices, and allow selective hearing in crowded rooms. This type of AR will be, he said, “an assistant, connected to the Internet, sitting on your shoulders, and feeding you useful information to your ears and eyes when you need it.”

X-Ray Tech Lays Chip Secrets Bare

Post Syndicated from Samuel K. Moore original https://spectrum.ieee.org/nanoclast/semiconductors/design/xray-tech-lays-chip-secrets-bare

Scientists and engineers in Switzerland and California have come up with a technique that can reveal the 3D design of a modern microprocessor without destroying it.

Typically today, such reverse engineering is a time-consuming process that involves painstakingly removing each of a chip’s many nanometers-thick interconnect layers and mapping them using a hierarchy of different imaging techniques, from optical microscopy for the larger features to electron microscopy for the tiniest features. 

The inventors of the new technique, called ptychographic X-ray laminography, say it could be used by integrated circuit designers to verify that manufactured chips match their designs, or by government agencies concerned about “kill switches” or hardware trojans that could have secretly been added to ICs they depend on.

“It’s the only approach to non-destructive reverse engineering of electronic chips—[and] not just reverse engineering but assurance that chips are manufactured according to design,” says Anthony F. J. Levi, professor of electrical and computer engineering at University of Southern California, who led the California side of the team. “You can identify the foundry, aspects of the design, who did the design. It’s like a fingerprint.”