Post Syndicated from original https://mjg59.dreamwidth.org/58879.html
I’ve been digging through the firmware for an AMD laptop with a Ryzen 6000 that incorporates Pluton for the past couple of weeks, and I’ve got some rough conclusions. Note that these are extremely preliminary and may not be accurate, but I’m going to try to encourage others to look into this in more detail. For those of you at home, I’m using an image from here, specifically version 309. The installer is happy to run under Wine, and if you tell it to “Extract” rather than “Install” it’ll leave a file sitting in C:\\DRIVERS\ASUS_GA402RK_309_BIOS_Update_20220322235241 which seems to have an additional 2K of header on it. Strip that and you should have something approximating a flash image.
Looking for UTF16 strings in this reveals something interesting:
Pluton (HSP) X86 Firmware Support
Enable/Disable X86 firmware HSP related code path, including AGESA HSP module, SBIOS HSP related drivers.
Auto - Depends on PcdAmdHspCoreEnable build value
NOTE: PSP directory entry 0xB BIT36 have the highest priority.
NOTE: This option will NOT put HSP hardware in disable state, to disable HSP hardware, you need setup PSP directory entry 0xB, BIT36 to 1.
// EntryValue[36] = 0: Enable, HSP core is enabled.
// EntryValue[36] = 1: Disable, HSP core is disabled then PSP will gate the HSP clock, no further PSP to HSP commands. System will boot without HSP.
“HSP” here means “Hardware Security Processor” – a generic term that refers to Pluton in this case. This is a configuration setting that determines whether Pluton is “enabled” or not – my interpretation of this is that it doesn’t directly influence Pluton, but disables all mechanisms that would allow the OS to communicate with it. In this scenario, Pluton has its firmware loaded and could conceivably be functional if the OS knew how to speak to it directly, but the firmware will never speak to it itself. I took a quick look at the Windows drivers for Pluton and it looks like they won’t do anything unless the firmware wants to expose Pluton, so this should mean that Windows will do nothing.
So what about the reference to “PSP directory entry 0xB BIT36 have the highest priority”? The PSP is the AMD Platform Security Processor – it’s an ARM core on the CPU package that boots before the x86. The PSP firmware lives in the same flash image as the x86 firmware, so the PSP looks for a header that points it towards the firmware it should execute. This gives a pointer to a “directory” – a list of different object types and where they’re located in flash (there’s a description of this for slightly older AMDs here). Type 0xb is treated slightly specially. Where most types contain the address of where the actual object is, type 0xb contains a 64-bit value that’s interpreted as enabling or disabling various features – something AMD calls “soft fusing” (Intel have something similar that involves setting bits in the Firmware Interface Table). The PSP looks at the bits that are set here and alters its behaviour. If bit 36 is set, the PSP tells Pluton to turn itself off and will no longer send any commands to it.
So, we have two mechanisms to disable Pluton – the PSP can tell it to turn itself off, or the x86 firmware can simply never speak to it or admit that it exists. Both of these imply that Pluton has started executing before it’s shut down, so it’s reasonable to wonder whether it can still do stuff. In the image I’m looking at, there’s a blob starting at 0x0069b610 that appears to be firmware for Pluton – it contains chunks that appear to be the reference TPM2 implementation, and it broadly decompiles as valid ARM code. It should be viable to figure out whether it can do anything in the face of being “disabled” via either of the above mechanisms.
Unfortunately for me, the system I’m looking at does set bit 36 in the 0xb entry – as a result, Pluton is disabled before x86 code starts running and I can’t investigate further in any straightforward way. The implication that the user-controllable mechanism for disabling Pluton merely disables x86 communication with it rather than turning it off entirely is a little concerning, although (assuming Pluton is behaving as a TPM rather than having an enhanced set of capabilities) skipping any firmware communication means the OS has no way to know what happened before it started running even if it has a mechanism to communicate with Pluton without firmware assistance. In that scenario it’d be viable to write a bootloader shim that just faked up the firmware measurements before handing control to the OS.
The bit 36 disabling mechanism seems more solid? Again, it should be possible to analyse the Pluton firmware to determine whether it actually pays attention to a disable command being sent. But even if it chooses to ignore that, if the PSP is in a position to just cut the clock to Pluton, it’s not going to be able to do a lot. At that point we’re trusting AMD rather than trusting Microsoft, but given that you’re also trusting AMD to execute the code you’re giving them to execute, it’s hard to avoid placing trust in them.
Overall: I’m reasonably confident that systems that ship with Pluton disabled via setting bit 36 in the soft fuses are going to disable it sufficiently hard that the OS can’t do anything about it. Systems that give the user an option to enable or disable it are a little less clear in that respect, and it’s possible (but not yet demonstrated) that an OS could communicate with Pluton anyway. However, if that’s true, and if the firmware never communicates with Pluton itself, the user could install a stub loader in UEFI that mimicks the firmware behaviour and leaves the OS thinking everything was good when it absolutely is not.
So, assuming that Pluton in its current form on AMD has no capabilities outside those we know about, the disabling mechanisms are probably good enough. It’s tough to make a firm statement on this before I have access to a system that doesn’t just disable it immediately, so stay tuned for updates.
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